From 0666a6ba1dbd66cf8b93c113e362ccbcd99152a0 Mon Sep 17 00:00:00 2001 From: Arne Dußin Date: Sat, 6 Nov 2021 11:50:33 +0100 Subject: Initial commit --- src/sercom0/spim/addr.rs | 138 ++++++ src/sercom0/spim/baud.rs | 102 +++++ src/sercom0/spim/ctrla.rs | 981 +++++++++++++++++++++++++++++++++++++++++++ src/sercom0/spim/ctrlb.rs | 433 +++++++++++++++++++ src/sercom0/spim/data.rs | 102 +++++ src/sercom0/spim/dbgctrl.rs | 112 +++++ src/sercom0/spim/intenclr.rs | 296 +++++++++++++ src/sercom0/spim/intenset.rs | 296 +++++++++++++ src/sercom0/spim/intflag.rs | 296 +++++++++++++ src/sercom0/spim/status.rs | 112 +++++ src/sercom0/spim/syncbusy.rs | 90 ++++ 11 files changed, 2958 insertions(+) create mode 100644 src/sercom0/spim/addr.rs create mode 100644 src/sercom0/spim/baud.rs create mode 100644 src/sercom0/spim/ctrla.rs create mode 100644 src/sercom0/spim/ctrlb.rs create mode 100644 src/sercom0/spim/data.rs create mode 100644 src/sercom0/spim/dbgctrl.rs create mode 100644 src/sercom0/spim/intenclr.rs create mode 100644 src/sercom0/spim/intenset.rs create mode 100644 src/sercom0/spim/intflag.rs create mode 100644 src/sercom0/spim/status.rs create mode 100644 src/sercom0/spim/syncbusy.rs (limited to 'src/sercom0/spim') diff --git a/src/sercom0/spim/addr.rs b/src/sercom0/spim/addr.rs new file mode 100644 index 0000000..c1892a3 --- /dev/null +++ b/src/sercom0/spim/addr.rs @@ -0,0 +1,138 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader); +impl ADDR_R { + pub(crate) fn new(bits: u8) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub struct ADDRMASK_R(crate::FieldReader); +impl ADDRMASK_R { + pub(crate) fn new(bits: u8) -> Self { + ADDRMASK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDRMASK_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub struct ADDRMASK_W<'a> { + w: &'a mut W, +} +impl<'a> ADDRMASK_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&mut self) -> ADDRMASK_W { + ADDRMASK_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/baud.rs b/src/sercom0/spim/baud.rs new file mode 100644 index 0000000..93cfeee --- /dev/null +++ b/src/sercom0/spim/baud.rs @@ -0,0 +1,102 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader); +impl BAUD_R { + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u8 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/ctrla.rs b/src/sercom0/spim/ctrla.rs new file mode 100644 index 0000000..4fc2d85 --- /dev/null +++ b/src/sercom0/spim/ctrla.rs @@ -0,0 +1,981 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader); +impl MODE_R { + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub struct RUNSTDBY_R(crate::FieldReader); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub struct IBON_R(crate::FieldReader); +impl IBON_R { + pub(crate) fn new(bits: bool) -> Self { + IBON_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for IBON_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub struct IBON_W<'a> { + w: &'a mut W, +} +impl<'a> IBON_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Data Out Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DOPO_A { + #[doc = "0: DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD0 = 0, + #[doc = "1: DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub struct DOPO_R(crate::FieldReader); +impl DOPO_R { + pub(crate) fn new(bits: u8) -> Self { + DOPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DOPO_A { + match self.bits { + 0 => DOPO_A::PAD0, + 1 => DOPO_A::PAD1, + 2 => DOPO_A::PAD2, + 3 => DOPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DOPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DOPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DOPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DOPO_A::PAD3 + } +} +impl core::ops::Deref for DOPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub struct DOPO_W<'a> { + w: &'a mut W, +} +impl<'a> DOPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DOPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DOPO_A::PAD0) + } + #[doc = "DO on PAD\\[2\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DOPO_A::PAD1) + } + #[doc = "DO on PAD\\[3\\], SCK on PAD\\[1\\] +and SS on PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DOPO_A::PAD2) + } + #[doc = "DO on PAD\\[0\\], SCK on PAD\\[3\\] +and SS on PAD\\[1\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DOPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Data In Pinout\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIPO_A { + #[doc = "0: SERCOM PAD\\[0\\]"] + PAD0 = 0, + #[doc = "1: SERCOM PAD\\[1\\]"] + PAD1 = 1, + #[doc = "2: SERCOM PAD\\[2\\]"] + PAD2 = 2, + #[doc = "3: SERCOM PAD\\[3\\]"] + PAD3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIPO_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub struct DIPO_R(crate::FieldReader); +impl DIPO_R { + pub(crate) fn new(bits: u8) -> Self { + DIPO_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIPO_A { + match self.bits { + 0 => DIPO_A::PAD0, + 1 => DIPO_A::PAD1, + 2 => DIPO_A::PAD2, + 3 => DIPO_A::PAD3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PAD0`"] + #[inline(always)] + pub fn is_pad0(&self) -> bool { + **self == DIPO_A::PAD0 + } + #[doc = "Checks if the value of the field is `PAD1`"] + #[inline(always)] + pub fn is_pad1(&self) -> bool { + **self == DIPO_A::PAD1 + } + #[doc = "Checks if the value of the field is `PAD2`"] + #[inline(always)] + pub fn is_pad2(&self) -> bool { + **self == DIPO_A::PAD2 + } + #[doc = "Checks if the value of the field is `PAD3`"] + #[inline(always)] + pub fn is_pad3(&self) -> bool { + **self == DIPO_A::PAD3 + } +} +impl core::ops::Deref for DIPO_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub struct DIPO_W<'a> { + w: &'a mut W, +} +impl<'a> DIPO_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIPO_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "SERCOM PAD\\[0\\]"] + #[inline(always)] + pub fn pad0(self) -> &'a mut W { + self.variant(DIPO_A::PAD0) + } + #[doc = "SERCOM PAD\\[1\\]"] + #[inline(always)] + pub fn pad1(self) -> &'a mut W { + self.variant(DIPO_A::PAD1) + } + #[doc = "SERCOM PAD\\[2\\]"] + #[inline(always)] + pub fn pad2(self) -> &'a mut W { + self.variant(DIPO_A::PAD2) + } + #[doc = "SERCOM PAD\\[3\\]"] + #[inline(always)] + pub fn pad3(self) -> &'a mut W { + self.variant(DIPO_A::PAD3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Frame Format\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FORM_A { + #[doc = "0: SPI Frame"] + SPI_FRAME = 0, + #[doc = "2: SPI Frame with Addr"] + SPI_FRAME_WITH_ADDR = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FORM_A) -> Self { + variant as _ + } +} +#[doc = "Field `FORM` reader - Frame Format"] +pub struct FORM_R(crate::FieldReader); +impl FORM_R { + pub(crate) fn new(bits: u8) -> Self { + FORM_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FORM_A::SPI_FRAME), + 2 => Some(FORM_A::SPI_FRAME_WITH_ADDR), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SPI_FRAME`"] + #[inline(always)] + pub fn is_spi_frame(&self) -> bool { + **self == FORM_A::SPI_FRAME + } + #[doc = "Checks if the value of the field is `SPI_FRAME_WITH_ADDR`"] + #[inline(always)] + pub fn is_spi_frame_with_addr(&self) -> bool { + **self == FORM_A::SPI_FRAME_WITH_ADDR + } +} +impl core::ops::Deref for FORM_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FORM` writer - Frame Format"] +pub struct FORM_W<'a> { + w: &'a mut W, +} +impl<'a> FORM_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FORM_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Frame"] + #[inline(always)] + pub fn spi_frame(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME) + } + #[doc = "SPI Frame with Addr"] + #[inline(always)] + pub fn spi_frame_with_addr(self) -> &'a mut W { + self.variant(FORM_A::SPI_FRAME_WITH_ADDR) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Clock Phase\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPHA_A { + #[doc = "0: The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + LEADING_EDGE = 0, + #[doc = "1: The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + TRAILING_EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPHA_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Phase"] +pub struct CPHA_R(crate::FieldReader); +impl CPHA_R { + pub(crate) fn new(bits: bool) -> Self { + CPHA_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPHA_A { + match self.bits { + false => CPHA_A::LEADING_EDGE, + true => CPHA_A::TRAILING_EDGE, + } + } + #[doc = "Checks if the value of the field is `LEADING_EDGE`"] + #[inline(always)] + pub fn is_leading_edge(&self) -> bool { + **self == CPHA_A::LEADING_EDGE + } + #[doc = "Checks if the value of the field is `TRAILING_EDGE`"] + #[inline(always)] + pub fn is_trailing_edge(&self) -> bool { + **self == CPHA_A::TRAILING_EDGE + } +} +impl core::ops::Deref for CPHA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPHA` writer - Clock Phase"] +pub struct CPHA_W<'a> { + w: &'a mut W, +} +impl<'a> CPHA_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPHA_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "The data is sampled on a leading SCK edge and changed on a trailing SCK edge"] + #[inline(always)] + pub fn leading_edge(self) -> &'a mut W { + self.variant(CPHA_A::LEADING_EDGE) + } + #[doc = "The data is sampled on a trailing SCK edge and changed on a leading SCK edge"] + #[inline(always)] + pub fn trailing_edge(self) -> &'a mut W { + self.variant(CPHA_A::TRAILING_EDGE) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28); + self.w + } +} +#[doc = "Clock Polarity\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum CPOL_A { + #[doc = "0: SCK is low when idle"] + IDLE_LOW = 0, + #[doc = "1: SCK is high when idle"] + IDLE_HIGH = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CPOL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub struct CPOL_R(crate::FieldReader); +impl CPOL_R { + pub(crate) fn new(bits: bool) -> Self { + CPOL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CPOL_A { + match self.bits { + false => CPOL_A::IDLE_LOW, + true => CPOL_A::IDLE_HIGH, + } + } + #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[inline(always)] + pub fn is_idle_low(&self) -> bool { + **self == CPOL_A::IDLE_LOW + } + #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[inline(always)] + pub fn is_idle_high(&self) -> bool { + **self == CPOL_A::IDLE_HIGH + } +} +impl core::ops::Deref for CPOL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub struct CPOL_W<'a> { + w: &'a mut W, +} +impl<'a> CPOL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPOL_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "SCK is low when idle"] + #[inline(always)] + pub fn idle_low(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_LOW) + } + #[doc = "SCK is high when idle"] + #[inline(always)] + pub fn idle_high(self) -> &'a mut W { + self.variant(CPOL_A::IDLE_HIGH) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29); + self.w + } +} +#[doc = "Data Order\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DORD_A { + #[doc = "0: MSB is transferred first"] + MSB = 0, + #[doc = "1: LSB is transferred first"] + LSB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DORD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DORD` reader - Data Order"] +pub struct DORD_R(crate::FieldReader); +impl DORD_R { + pub(crate) fn new(bits: bool) -> Self { + DORD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DORD_A { + match self.bits { + false => DORD_A::MSB, + true => DORD_A::LSB, + } + } + #[doc = "Checks if the value of the field is `MSB`"] + #[inline(always)] + pub fn is_msb(&self) -> bool { + **self == DORD_A::MSB + } + #[doc = "Checks if the value of the field is `LSB`"] + #[inline(always)] + pub fn is_lsb(&self) -> bool { + **self == DORD_A::LSB + } +} +impl core::ops::Deref for DORD_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DORD` writer - Data Order"] +pub struct DORD_W<'a> { + w: &'a mut W, +} +impl<'a> DORD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DORD_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "MSB is transferred first"] + #[inline(always)] + pub fn msb(self) -> &'a mut W { + self.variant(DORD_A::MSB) + } + #[doc = "LSB is transferred first"] + #[inline(always)] + pub fn lsb(self) -> &'a mut W { + self.variant(DORD_A::LSB) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 0x01) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 0x01) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&mut self) -> IBON_W { + IBON_W { w: self } + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&mut self) -> DOPO_W { + DOPO_W { w: self } + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&mut self) -> DIPO_W { + DIPO_W { w: self } + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&mut self) -> FORM_W { + FORM_W { w: self } + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&mut self) -> CPHA_W { + CPHA_W { w: self } + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&mut self) -> CPOL_W { + CPOL_W { w: self } + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&mut self) -> DORD_W { + DORD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/ctrlb.rs b/src/sercom0/spim/ctrlb.rs new file mode 100644 index 0000000..f8fe32f --- /dev/null +++ b/src/sercom0/spim/ctrlb.rs @@ -0,0 +1,433 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Character Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CHSIZE_A { + #[doc = "0: 8 bits"] + _8_BIT = 0, + #[doc = "1: 9 bits"] + _9_BIT = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub struct CHSIZE_R(crate::FieldReader); +impl CHSIZE_R { + pub(crate) fn new(bits: u8) -> Self { + CHSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CHSIZE_A::_8_BIT), + 1 => Some(CHSIZE_A::_9_BIT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_8_BIT`"] + #[inline(always)] + pub fn is_8_bit(&self) -> bool { + **self == CHSIZE_A::_8_BIT + } + #[doc = "Checks if the value of the field is `_9_BIT`"] + #[inline(always)] + pub fn is_9_bit(&self) -> bool { + **self == CHSIZE_A::_9_BIT + } +} +impl core::ops::Deref for CHSIZE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHSIZE` writer - Character Size"] +pub struct CHSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CHSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CHSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8 bits"] + #[inline(always)] + pub fn _8_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_8_BIT) + } + #[doc = "9 bits"] + #[inline(always)] + pub fn _9_bit(self) -> &'a mut W { + self.variant(CHSIZE_A::_9_BIT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub struct PLOADEN_R(crate::FieldReader); +impl PLOADEN_R { + pub(crate) fn new(bits: bool) -> Self { + PLOADEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PLOADEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub struct PLOADEN_W<'a> { + w: &'a mut W, +} +impl<'a> PLOADEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub struct SSDE_R(crate::FieldReader); +impl SSDE_R { + pub(crate) fn new(bits: bool) -> Self { + SSDE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSDE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub struct SSDE_W<'a> { + w: &'a mut W, +} +impl<'a> SSDE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub struct MSSEN_R(crate::FieldReader); +impl MSSEN_R { + pub(crate) fn new(bits: bool) -> Self { + MSSEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MSSEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub struct MSSEN_W<'a> { + w: &'a mut W, +} +impl<'a> MSSEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Address Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum AMODE_A { + #[doc = "0: SPI Address mask "] + MASK = 0, + #[doc = "1: Two unique Addressess"] + _2_ADDRESSES = 1, + #[doc = "2: Address Range"] + RANGE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AMODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `AMODE` reader - Address Mode"] +pub struct AMODE_R(crate::FieldReader); +impl AMODE_R { + pub(crate) fn new(bits: u8) -> Self { + AMODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(AMODE_A::MASK), + 1 => Some(AMODE_A::_2_ADDRESSES), + 2 => Some(AMODE_A::RANGE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + **self == AMODE_A::MASK + } + #[doc = "Checks if the value of the field is `_2_ADDRESSES`"] + #[inline(always)] + pub fn is_2_addresses(&self) -> bool { + **self == AMODE_A::_2_ADDRESSES + } + #[doc = "Checks if the value of the field is `RANGE`"] + #[inline(always)] + pub fn is_range(&self) -> bool { + **self == AMODE_A::RANGE + } +} +impl core::ops::Deref for AMODE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMODE` writer - Address Mode"] +pub struct AMODE_W<'a> { + w: &'a mut W, +} +impl<'a> AMODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: AMODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "SPI Address mask"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(AMODE_A::MASK) + } + #[doc = "Two unique Addressess"] + #[inline(always)] + pub fn _2_addresses(self) -> &'a mut W { + self.variant(AMODE_A::_2_ADDRESSES) + } + #[doc = "Address Range"] + #[inline(always)] + pub fn range(self) -> &'a mut W { + self.variant(AMODE_A::RANGE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 14)) | ((value as u32 & 0x03) << 14); + self.w + } +} +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub struct RXEN_R(crate::FieldReader); +impl RXEN_R { + pub(crate) fn new(bits: bool) -> Self { + RXEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXEN_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub struct RXEN_W<'a> { + w: &'a mut W, +} +impl<'a> RXEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 0x03) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&mut self) -> CHSIZE_W { + CHSIZE_W { w: self } + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&mut self) -> PLOADEN_W { + PLOADEN_W { w: self } + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&mut self) -> SSDE_W { + SSDE_W { w: self } + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&mut self) -> MSSEN_W { + MSSEN_W { w: self } + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&mut self) -> AMODE_W { + AMODE_W { w: self } + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&mut self) -> RXEN_W { + RXEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/data.rs b/src/sercom0/spim/data.rs new file mode 100644 index 0000000..66fa416 --- /dev/null +++ b/src/sercom0/spim/data.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader); +impl DATA_R { + pub(crate) fn new(bits: u16) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01ff) | (value as u32 & 0x01ff); + self.w + } +} +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/dbgctrl.rs b/src/sercom0/spim/dbgctrl.rs new file mode 100644 index 0000000..5c489c9 --- /dev/null +++ b/src/sercom0/spim/dbgctrl.rs @@ -0,0 +1,112 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader); +impl DBGSTOP_R { + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/intenclr.rs b/src/sercom0/spim/intenclr.rs new file mode 100644 index 0000000..7c7cc32 --- /dev/null +++ b/src/sercom0/spim/intenclr.rs @@ -0,0 +1,296 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/intenset.rs b/src/sercom0/spim/intenset.rs new file mode 100644 index 0000000..68cf83d --- /dev/null +++ b/src/sercom0/spim/intenset.rs @@ -0,0 +1,296 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/intflag.rs b/src/sercom0/spim/intflag.rs new file mode 100644 index 0000000..d3b6dbb --- /dev/null +++ b/src/sercom0/spim/intflag.rs @@ -0,0 +1,296 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub struct DRE_R(crate::FieldReader); +impl DRE_R { + pub(crate) fn new(bits: bool) -> Self { + DRE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DRE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DRE` writer - Data Register Empty Interrupt"] +pub struct DRE_W<'a> { + w: &'a mut W, +} +impl<'a> DRE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub struct TXC_R(crate::FieldReader); +impl TXC_R { + pub(crate) fn new(bits: bool) -> Self { + TXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub struct TXC_W<'a> { + w: &'a mut W, +} +impl<'a> TXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub struct RXC_R(crate::FieldReader); +impl RXC_R { + pub(crate) fn new(bits: bool) -> Self { + RXC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXC_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXC` writer - Receive Complete Interrupt"] +pub struct RXC_W<'a> { + w: &'a mut W, +} +impl<'a> RXC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub struct SSL_R(crate::FieldReader); +impl SSL_R { + pub(crate) fn new(bits: bool) -> Self { + SSL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SSL_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub struct SSL_W<'a> { + w: &'a mut W, +} +impl<'a> SSL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&mut self) -> DRE_W { + DRE_W { w: self } + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&mut self) -> TXC_W { + TXC_W { w: self } + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&mut self) -> RXC_W { + RXC_W { w: self } + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&mut self) -> SSL_W { + SSL_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/status.rs b/src/sercom0/spim/status.rs new file mode 100644 index 0000000..34b72da --- /dev/null +++ b/src/sercom0/spim/status.rs @@ -0,0 +1,112 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub struct BUFOVF_R(crate::FieldReader); +impl BUFOVF_R { + pub(crate) fn new(bits: bool) -> Self { + BUFOVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUFOVF_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub struct BUFOVF_W<'a> { + w: &'a mut W, +} +impl<'a> BUFOVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&mut self) -> BUFOVF_W { + BUFOVF_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPIM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/spim/syncbusy.rs b/src/sercom0/spim/syncbusy.rs new file mode 100644 index 0000000..fb0b565 --- /dev/null +++ b/src/sercom0/spim/syncbusy.rs @@ -0,0 +1,90 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub struct CTRLB_R(crate::FieldReader); +impl CTRLB_R { + pub(crate) fn new(bits: bool) -> Self { + CTRLB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CTRLB_R { + type Target = crate::FieldReader; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "SPIM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} -- cgit v1.2.3-70-g09d2