Microchip Technology MCHP ATSAMC21N18A SAMC21 0 Microchip ATSAMC21N18A Microcontroller CM0+ r0p0 selectable true false 2 false 8 32 32 read-write 0x00000000 0xFFFFFFFF AC U22451.1.1 Analog Comparators AC AC_ 0x42005000 0 0x24 registers AC 27 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B 0x1 8 write-only 0x00 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 START2 Comparator 2 Start Comparison 2 1 START3 Comparator 3 Start Comparison 3 1 EVCTRL Event Control 0x2 16 0x0000 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 COMPEO2 Comparator 2 Event Output Enable 2 1 COMPEO3 Comparator 3 Event Output Enable 3 1 WINEO0 Window 0 Event Output Enable 4 1 WINEO1 Window 1 Event Output Enable 5 1 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 COMPEI2 Comparator 2 Event Input Enable 10 1 COMPEI3 Comparator 3 Event Input Enable 11 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 INVEI2 Comparator 2 Input Event Invert Enable 14 1 INVEI3 Comparator 3 Input Event Invert Enable 15 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 COMP2 Comparator 2 Interrupt Enable 2 1 COMP3 Comparator 3 Interrupt Enable 3 1 WIN0 Window 0 Interrupt Enable 4 1 WIN1 Window 1 Interrupt Enable 5 1 INTENSET Interrupt Enable Set 0x5 8 0x00 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 COMP2 Comparator 2 Interrupt Enable 2 1 COMP3 Comparator 3 Interrupt Enable 3 1 WIN0 Window 0 Interrupt Enable 4 1 WIN1 Window 1 Interrupt Enable 5 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 COMP2 Comparator 2 2 1 COMP3 Comparator 3 3 1 WIN0 Window 0 4 1 WIN1 Window 1 5 1 STATUSA Status A 0x7 8 read-only 0x00 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 STATE2 Comparator 2 Current State 2 1 STATE3 Comparator 3 Current State 3 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0 INSIDE Signal is inside window 1 BELOW Signal is below window 2 WSTATE1 Window 1 Current State 6 2 WSTATE1Select ABOVE Signal is above window 0 INSIDE Signal is inside window 1 BELOW Signal is below window 2 STATUSB Status B 0x8 8 read-only 0x00 READY0 Comparator 0 Ready 0 1 READY1 Comparator 1 Ready 1 1 READY2 Comparator 2 Ready 2 1 READY3 Comparator 3 Ready 3 1 DBGCTRL Debug Control 0x9 8 0x00 DBGRUN Debug Run 0 1 WINCTRL Window Control 0xA 8 0x00 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0 INSIDE Interrupt on signal inside window 1 BELOW Interrupt on signal below window 2 OUTSIDE Interrupt on signal outside window 3 WEN1 Window 1 Mode Enable 4 1 WINTSEL1 Window 1 Interrupt Selection 5 2 WINTSEL1Select ABOVE Interrupt on signal above window 0 INSIDE Interrupt on signal inside window 1 BELOW Interrupt on signal below window 2 OUTSIDE Interrupt on signal outside window 3 4 1 SCALER[%s] Scaler n 0xC 8 0x00 VALUE Scaler Value 0 6 4 4 COMPCTRL[%s] Comparator Control n 0x10 32 0x00000000 ENABLE Enable 1 1 SINGLE Single-Shot Mode 2 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 RUNSTDBY Run in Standby 6 1 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 SWAP Swap Inputs and Invert 15 1 SPEED Speed Selection 16 2 SPEEDSelect LOW Low speed 0 HIGH High speed 3 HYSTEN Hysteresis Enable 19 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 SYNCBUSY Synchronization Busy 0x20 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE Enable Synchronization Busy 1 1 WINCTRL WINCTRL Synchronization Busy 2 1 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 COMPCTRL2 COMPCTRL 2 Synchronization Busy 5 1 COMPCTRL3 COMPCTRL 3 Synchronization Busy 6 1 ADC0 U22472.3.0 Analog Digital Converter ADC ADC_ 0x42004400 0 0x2E registers ADC0 25 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 SLAVEEN Slave Enable 5 1 RUNSTDBY Run During Standby 6 1 ONDEMAND On Demand Control 7 1 CTRLB Control B 0x1 8 0x00 PRESCALER Prescaler Configuration 0 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 REFCTRL Reference Control 0x2 8 0x00 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/1.6 VDDANA 0x1 INTVCC1 1/2 VDDANA 0x2 AREFA External Reference 0x3 DAC DAC 0x4 INTVCC2 VDDANA 0x5 REFCOMP Reference Buffer Offset Compensation Enable 7 1 EVCTRL Event Control 0x3 8 0x00 FLUSHEI Flush Event Input Enable 0 1 STARTEI Start Conversion Event Input Enable 1 1 FLUSHINV Flush Event Invert Enable 2 1 STARTINV Start Event Invert Enable 3 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 RESRDY Result Ready Interrupt Disable 0 1 OVERRUN Overrun Interrupt Disable 1 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x5 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 RESRDY Result Ready Interrupt Flag 0 1 OVERRUN Overrun Interrupt Flag 1 1 WINMON Window Monitor Interrupt Flag 2 1 SEQSTATUS Sequence Status 0x7 8 read-only 0x00 SEQSTATE Sequence State 0 5 SEQBUSY Sequence Busy 7 1 INPUTCTRL Input Control 0x8 16 0x0000 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB TEMP Temperature Sensor 0x18 BANDGAP Bandgap Voltage 0x19 SCALEDCOREVCC 1/4 Scaled Core Supply 0x1A SCALEDIOVCC 1/4 Scaled I/O Supply 0x1B DAC DAC Output 0x1C MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 GND Internal Ground 0x18 CTRLC Control C 0xA 16 0x0000 DIFFMODE Differential Mode 0 1 LEFTADJ Left-Adjusted Result 1 1 FREERUN Free Running Mode 2 1 CORREN Digital Correction Logic Enable 3 1 RESSEL Conversion Result Resolution 4 2 RESSELSelect 12BIT 12-bit 0x0 16BIT 16-bit averaging mode 0x1 10BIT 10-bit 0x2 8BIT 8-bit 0x3 R2R Rail-to-Rail mode enable 7 1 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 DUALSEL Dual Mode Trigger Selection 12 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 AVGCTRL Average Control 0xC 8 0x00 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA ADJRES Adjusting Result / Division Coefficient 4 3 SAMPCTRL Sample Time Control 0xD 8 0x00 SAMPLEN Sampling Time Length 0 6 OFFCOMP Comparator Offset Compensation Enable 7 1 WINLT Window Monitor Lower Threshold 0xE 16 0x0000 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0x10 16 0x0000 WINUT Window Upper Threshold 0 16 GAINCORR Gain Correction 0x12 16 0x0000 GAINCORR Gain Correction Value 0 12 OFFSETCORR Offset Correction 0x14 16 0x0000 OFFSETCORR Offset Correction Value 0 12 SWTRIG Software Trigger 0x18 8 0x00 FLUSH ADC Flush 0 1 START Start ADC Conversion 1 1 DBGCTRL Debug Control 0x1C 8 0x00 DBGRUN Debug Run 0 1 SYNCBUSY Synchronization Busy 0x20 16 read-only 0x0000 SWRST SWRST Synchronization Busy 0 1 ENABLE ENABLE Synchronization Busy 1 1 INPUTCTRL INPUTCTRL Synchronization Busy 2 1 CTRLC CTRLC Synchronization Busy 3 1 AVGCTRL AVGCTRL Synchronization Busy 4 1 SAMPCTRL SAMPCTRL Synchronization Busy 5 1 WINLT WINLT Synchronization Busy 6 1 WINUT WINUT Synchronization Busy 7 1 GAINCORR GAINCORR Synchronization Busy 8 1 OFFSETCORR OFFSETCTRL Synchronization Busy 9 1 SWTRIG SWTRG Synchronization Busy 10 1 RESULT Result 0x24 16 read-only 0x0000 RESULT Result Value 0 16 SEQCTRL Sequence Control 0x28 32 0x00000000 SEQEN Enable Positive Input in the Sequence 0 32 CALIB Calibration 0x2C 16 0x0000 BIASCOMP Bias Comparator Scaling 0 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC1 0x42004800 ADC1 26 CAN0 U20032.0.0 Control Area Network CAN CAN_ 0x42001C00 0 0xFC registers CAN0 15 CREL Core Release 0x0 32 read-only 0x32100000 SUBSTEP Sub-step of Core Release 20 4 STEP Step of Core Release 24 4 REL Core Release 28 4 ENDN Endian 0x4 32 read-only 0x87654321 ETV Endianness Test Value 0 32 MRCFG Message RAM Configuration 0x8 32 0x00000002 QOS Quality of Service 0 2 QOSSelect DISABLE Background (no sensitive operation) 0 LOW Sensitive Bandwidth 1 MEDIUM Sensitive Latency 2 HIGH Critical Latency 3 DBTP Fast Bit Timing and Prescaler 0xC 32 0x00000A33 DSJW Data (Re)Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment before sample point 8 5 DBRP Data Baud Rate Prescaler 16 5 TDC Tranceiver Delay Compensation 23 1 TEST Test 0x10 32 0x00000000 LBCK Loop Back Mode 4 1 TX Control of Transmit Pin 5 2 TXSelect CORE TX controlled by CAN core 0 SAMPLE TX monitoring sample point 1 DOMINANT Dominant (0) level at pin CAN_TX 2 RECESSIVE Recessive (1) level at pin CAN_TX 3 RX Receive Pin 7 1 RWD RAM Watchdog 0x14 32 0x00000000 WDC Watchdog Configuration 0 8 WDV Watchdog Value 8 8 CCCR CC Control 0x18 32 0x00000001 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BRSE Bit Rate Switch Enable 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP Transmit Pause 14 1 NISO Non ISO Operation 15 1 NBTP Nominal Bit Timing and Prescaler 0x1C 32 0x06000A03 NTSEG2 Nominal Time segment after sample point 0 7 NTSEG1 Nominal Time segment before sample point 8 8 NBRP Nominal Baud Rate Prescaler 16 9 NSJW Nominal (Re)Synchronization Jump Width 25 7 TSCC Timestamp Counter Configuration 0x20 32 0x00000000 TSS Timestamp Select 0 2 TSSSelect ZERO Timestamp counter value always 0x0000 0 INC Timestamp counter value incremented by TCP 1 EXT External timestamp counter value used 2 TCP Timestamp Counter Prescaler 16 4 TSCV Timestamp Counter Value 0x24 32 read-only 0x00000000 TSC Timestamp Counter 0 16 TOCC Timeout Counter Configuration 0x28 32 0xFFFF0000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOSSelect CONT Continuout operation 0 TXEF Timeout controlled by TX Event FIFO 1 RXF0 Timeout controlled by Rx FIFO 0 2 RXF1 Timeout controlled by Rx FIFO 1 3 TOP Timeout Period 16 16 TOCV Timeout Counter Value 0x2C 32 0x0000FFFF TOC Timeout Counter 0 16 ECR Error Counter 0x40 32 read-only 0x00000000 TEC Transmit Error Counter 0 8 REC Receive Error Counter 8 7 RP Receive Error Passive 15 1 CEL CAN Error Logging 16 8 PSR Protocol Status 0x44 32 read-only 0x00000707 LEC Last Error Code 0 3 LECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 ACT Activity 3 2 ACTSelect SYNC Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RX Node is operating as receiver 2 TX Node is operating as transmitter 3 EP Error Passive 5 1 EW Warning Status 6 1 BO Bus_Off Status 7 1 DLEC Data Phase Last Error Code 8 3 DLECSelect NONE No Error 0 STUFF Stuff Error 1 FORM Form Error 2 ACK Ack Error 3 BIT1 Bit1 Error 4 BIT0 Bit0 Error 5 CRC CRC Error 6 NC No Change 7 RESI ESI flag of last received CAN FD Message 11 1 RBRS BRS flag of last received CAN FD Message 12 1 RFDF Received a CAN FD Message 13 1 PXE Protocol Exception Event 14 1 TDCV Transmitter Delay Compensation Value 16 7 TDCR Extended ID Filter Configuration 0x48 32 0x00000000 TDCF Transmitter Delay Compensation Filter Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 IR Interrupt 0x50 32 0x00000000 RF0N Rx FIFO 0 New Message 0 1 RF0W Rx FIFO 0 Watermark Reached 1 1 RF0F Rx FIFO 0 Full 2 1 RF0L Rx FIFO 0 Message Lost 3 1 RF1N Rx FIFO 1 New Message 4 1 RF1W Rx FIFO 1 Watermark Reached 5 1 RF1F Rx FIFO 1 FIFO Full 6 1 RF1L Rx FIFO 1 Message Lost 7 1 HPM High Priority Message 8 1 TC Timestamp Completed 9 1 TCF Transmission Cancellation Finished 10 1 TFE Tx FIFO Empty 11 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TSW Timestamp Wraparound 16 1 MRAF Message RAM Access Failure 17 1 TOO Timeout Occurred 18 1 DRX Message stored to Dedicated Rx Buffer 19 1 BEC Bit Error Corrected 20 1 BEU Bit Error Uncorrected 21 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 BO Bus_Off Status 25 1 WDI Watchdog Interrupt 26 1 PEA Protocol Error in Arbitration Phase 27 1 PED Protocol Error in Data Phase 28 1 ARA Access to Reserved Address 29 1 IE Interrupt Enable 0x54 32 0x00000000 RF0NE Rx FIFO 0 New Message Interrupt Enable 0 1 RF0WE Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF0FE Rx FIFO 0 Full Interrupt Enable 2 1 RF0LE Rx FIFO 0 Message Lost Interrupt Enable 3 1 RF1NE Rx FIFO 1 New Message Interrupt Enable 4 1 RF1WE Rx FIFO 1 Watermark Reached Interrupt Enable 5 1 RF1FE Rx FIFO 1 FIFO Full Interrupt Enable 6 1 RF1LE Rx FIFO 1 Message Lost Interrupt Enable 7 1 HPME High Priority Message Interrupt Enable 8 1 TCE Timestamp Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Element Lost Interrupt Enable 15 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 TOOE Timeout Occurred Interrupt Enable 18 1 DRXE Message stored to Dedicated Rx Buffer Interrupt Enable 19 1 BECE Bit Error Corrected Interrupt Enable 20 1 BEUE Bit Error Uncorrected Interrupt Enable 21 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 BOE Bus_Off Status Interrupt Enable 25 1 WDIE Watchdog Interrupt Interrupt Enable 26 1 PEAE Protocol Error in Arbitration Phase Enable 27 1 PEDE Protocol Error in Data Phase Enable 28 1 ARAE Access to Reserved Address Enable 29 1 ILS Interrupt Line Select 0x58 32 0x00000000 RF0NL Rx FIFO 0 New Message Interrupt Line 0 1 RF0WL Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF0FL Rx FIFO 0 Full Interrupt Line 2 1 RF0LL Rx FIFO 0 Message Lost Interrupt Line 3 1 RF1NL Rx FIFO 1 New Message Interrupt Line 4 1 RF1WL Rx FIFO 1 Watermark Reached Interrupt Line 5 1 RF1FL Rx FIFO 1 FIFO Full Interrupt Line 6 1 RF1LL Rx FIFO 1 Message Lost Interrupt Line 7 1 HPML High Priority Message Interrupt Line 8 1 TCL Timestamp Completed Interrupt Line 9 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Element Lost Interrupt Line 15 1 TSWL Timestamp Wraparound Interrupt Line 16 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 TOOL Timeout Occurred Interrupt Line 18 1 DRXL Message stored to Dedicated Rx Buffer Interrupt Line 19 1 BECL Bit Error Corrected Interrupt Line 20 1 BEUL Bit Error Uncorrected Interrupt Line 21 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 BOL Bus_Off Status Interrupt Line 25 1 WDIL Watchdog Interrupt Interrupt Line 26 1 PEAL Protocol Error in Arbitration Phase Line 27 1 PEDL Protocol Error in Data Phase Line 28 1 ARAL Access to Reserved Address Line 29 1 ILE Interrupt Line Enable 0x5C 32 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 GFC Global Filter Configuration 0x80 32 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RXF0 Accept in Rx FIFO 0 0 RXF1 Accept in Rx FIFO 1 1 REJECT Reject 2 SIDFC Standard ID Filter Configuration 0x84 32 0x00000000 FLSSA Filter List Standard Start Address 0 16 LSS List Size Standard 16 8 XIDFC Extended ID Filter Configuration 0x88 32 0x00000000 FLESA Filter List Extended Start Address 0 16 LSE List Size Extended 16 7 XIDAM Extended ID AND Mask 0x90 32 0x1FFFFFFF EIDM Extended ID Mask 0 29 HPMS High Priority Message Status 0x94 32 read-only 0x00000000 BIDX Buffer Index 0 6 MSI Message Storage Indicator 6 2 MSISelect NONE No FIFO selected 0 LOST FIFO message lost 1 FIFO0 Message stored in FIFO 0 2 FIFO1 Message stored in FIFO 1 3 FIDX Filter Index 8 7 FLST Filter List 15 1 NDAT1 New Data 1 0x98 32 0x00000000 ND0 New Data 0 0 1 ND1 New Data 1 1 1 ND2 New Data 2 2 1 ND3 New Data 3 3 1 ND4 New Data 4 4 1 ND5 New Data 5 5 1 ND6 New Data 6 6 1 ND7 New Data 7 7 1 ND8 New Data 8 8 1 ND9 New Data 9 9 1 ND10 New Data 10 10 1 ND11 New Data 11 11 1 ND12 New Data 12 12 1 ND13 New Data 13 13 1 ND14 New Data 14 14 1 ND15 New Data 15 15 1 ND16 New Data 16 16 1 ND17 New Data 17 17 1 ND18 New Data 18 18 1 ND19 New Data 19 19 1 ND20 New Data 20 20 1 ND21 New Data 21 21 1 ND22 New Data 22 22 1 ND23 New Data 23 23 1 ND24 New Data 24 24 1 ND25 New Data 25 25 1 ND26 New Data 26 26 1 ND27 New Data 27 27 1 ND28 New Data 28 28 1 ND29 New Data 29 29 1 ND30 New Data 30 30 1 ND31 New Data 31 31 1 NDAT2 New Data 2 0x9C 32 0x00000000 ND32 New Data 32 0 1 ND33 New Data 33 1 1 ND34 New Data 34 2 1 ND35 New Data 35 3 1 ND36 New Data 36 4 1 ND37 New Data 37 5 1 ND38 New Data 38 6 1 ND39 New Data 39 7 1 ND40 New Data 40 8 1 ND41 New Data 41 9 1 ND42 New Data 42 10 1 ND43 New Data 43 11 1 ND44 New Data 44 12 1 ND45 New Data 45 13 1 ND46 New Data 46 14 1 ND47 New Data 47 15 1 ND48 New Data 48 16 1 ND49 New Data 49 17 1 ND50 New Data 50 18 1 ND51 New Data 51 19 1 ND52 New Data 52 20 1 ND53 New Data 53 21 1 ND54 New Data 54 22 1 ND55 New Data 55 23 1 ND56 New Data 56 24 1 ND57 New Data 57 25 1 ND58 New Data 58 26 1 ND59 New Data 59 27 1 ND60 New Data 60 28 1 ND61 New Data 61 29 1 ND62 New Data 62 30 1 ND63 New Data 63 31 1 RXF0C Rx FIFO 0 Configuration 0xA0 32 0x00000000 F0SA Rx FIFO 0 Start Address 0 16 F0S Rx FIFO 0 Size 16 7 F0WM Rx FIFO 0 Watermark 24 7 F0OM FIFO 0 Operation Mode 31 1 RXF0S Rx FIFO 0 Status 0xA4 32 read-only 0x00000000 F0FL Rx FIFO 0 Fill Level 0 7 F0GI Rx FIFO 0 Get Index 8 6 F0PI Rx FIFO 0 Put Index 16 6 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 RXF0A Rx FIFO 0 Acknowledge 0xA8 32 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 6 RXBC Rx Buffer Configuration 0xAC 32 0x00000000 RBSA Rx Buffer Start Address 0 16 RXF1C Rx FIFO 1 Configuration 0xB0 32 0x00000000 F1SA Rx FIFO 1 Start Address 0 16 F1S Rx FIFO 1 Size 16 7 F1WM Rx FIFO 1 Watermark 24 7 F1OM FIFO 1 Operation Mode 31 1 RXF1S Rx FIFO 1 Status 0xB4 32 read-only 0x00000000 F1FL Rx FIFO 1 Fill Level 0 7 F1GI Rx FIFO 1 Get Index 8 6 F1PI Rx FIFO 1 Put Index 16 6 F1F Rx FIFO 1 Full 24 1 RF1L Rx FIFO 1 Message Lost 25 1 DMS Debug Message Status 30 2 DMSSelect IDLE Idle state 0 DBGA Debug message A received 1 DBGB Debug message A/B received 2 DBGC Debug message A/B/C received, DMA request set 3 RXF1A Rx FIFO 1 Acknowledge 0xB8 32 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 6 RXESC Rx Buffer / FIFO Element Size Configuration 0xBC 32 0x00000000 F0DS Rx FIFO 0 Data Field Size 0 3 F0DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 F1DS Rx FIFO 1 Data Field Size 4 3 F1DSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 RBDS Rx Buffer Data Field Size 8 3 RBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 TXBC Tx Buffer Configuration 0xC0 32 0x00000000 TBSA Tx Buffers Start Address 0 16 NDTB Number of Dedicated Transmit Buffers 16 6 TFQS Transmit FIFO/Queue Size 24 6 TFQM Tx FIFO/Queue Mode 30 1 TXFQS Tx FIFO / Queue Status 0xC4 32 read-only 0x00000000 TFFL Tx FIFO Free Level 0 6 TFGI Tx FIFO Get Index 8 5 TFQPI Tx FIFO/Queue Put Index 16 5 TFQF Tx FIFO/Queue Full 21 1 TXESC Tx Buffer Element Size Configuration 0xC8 32 0x00000000 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect DATA8 8 byte data field 0 DATA12 12 byte data field 1 DATA16 16 byte data field 2 DATA20 20 byte data field 3 DATA24 24 byte data field 4 DATA32 32 byte data field 5 DATA48 48 byte data field 6 DATA64 64 byte data field 7 TXBRP Tx Buffer Request Pending 0xCC 32 read-only 0x00000000 TRP0 Transmission Request Pending 0 0 1 TRP1 Transmission Request Pending 1 1 1 TRP2 Transmission Request Pending 2 2 1 TRP3 Transmission Request Pending 3 3 1 TRP4 Transmission Request Pending 4 4 1 TRP5 Transmission Request Pending 5 5 1 TRP6 Transmission Request Pending 6 6 1 TRP7 Transmission Request Pending 7 7 1 TRP8 Transmission Request Pending 8 8 1 TRP9 Transmission Request Pending 9 9 1 TRP10 Transmission Request Pending 10 10 1 TRP11 Transmission Request Pending 11 11 1 TRP12 Transmission Request Pending 12 12 1 TRP13 Transmission Request Pending 13 13 1 TRP14 Transmission Request Pending 14 14 1 TRP15 Transmission Request Pending 15 15 1 TRP16 Transmission Request Pending 16 16 1 TRP17 Transmission Request Pending 17 17 1 TRP18 Transmission Request Pending 18 18 1 TRP19 Transmission Request Pending 19 19 1 TRP20 Transmission Request Pending 20 20 1 TRP21 Transmission Request Pending 21 21 1 TRP22 Transmission Request Pending 22 22 1 TRP23 Transmission Request Pending 23 23 1 TRP24 Transmission Request Pending 24 24 1 TRP25 Transmission Request Pending 25 25 1 TRP26 Transmission Request Pending 26 26 1 TRP27 Transmission Request Pending 27 27 1 TRP28 Transmission Request Pending 28 28 1 TRP29 Transmission Request Pending 29 29 1 TRP30 Transmission Request Pending 30 30 1 TRP31 Transmission Request Pending 31 31 1 TXBAR Tx Buffer Add Request 0xD0 32 0x00000000 AR0 Add Request 0 0 1 AR1 Add Request 1 1 1 AR2 Add Request 2 2 1 AR3 Add Request 3 3 1 AR4 Add Request 4 4 1 AR5 Add Request 5 5 1 AR6 Add Request 6 6 1 AR7 Add Request 7 7 1 AR8 Add Request 8 8 1 AR9 Add Request 9 9 1 AR10 Add Request 10 10 1 AR11 Add Request 11 11 1 AR12 Add Request 12 12 1 AR13 Add Request 13 13 1 AR14 Add Request 14 14 1 AR15 Add Request 15 15 1 AR16 Add Request 16 16 1 AR17 Add Request 17 17 1 AR18 Add Request 18 18 1 AR19 Add Request 19 19 1 AR20 Add Request 20 20 1 AR21 Add Request 21 21 1 AR22 Add Request 22 22 1 AR23 Add Request 23 23 1 AR24 Add Request 24 24 1 AR25 Add Request 25 25 1 AR26 Add Request 26 26 1 AR27 Add Request 27 27 1 AR28 Add Request 28 28 1 AR29 Add Request 29 29 1 AR30 Add Request 30 30 1 AR31 Add Request 31 31 1 TXBCR Tx Buffer Cancellation Request 0xD4 32 0x00000000 CR0 Cancellation Request 0 0 1 CR1 Cancellation Request 1 1 1 CR2 Cancellation Request 2 2 1 CR3 Cancellation Request 3 3 1 CR4 Cancellation Request 4 4 1 CR5 Cancellation Request 5 5 1 CR6 Cancellation Request 6 6 1 CR7 Cancellation Request 7 7 1 CR8 Cancellation Request 8 8 1 CR9 Cancellation Request 9 9 1 CR10 Cancellation Request 10 10 1 CR11 Cancellation Request 11 11 1 CR12 Cancellation Request 12 12 1 CR13 Cancellation Request 13 13 1 CR14 Cancellation Request 14 14 1 CR15 Cancellation Request 15 15 1 CR16 Cancellation Request 16 16 1 CR17 Cancellation Request 17 17 1 CR18 Cancellation Request 18 18 1 CR19 Cancellation Request 19 19 1 CR20 Cancellation Request 20 20 1 CR21 Cancellation Request 21 21 1 CR22 Cancellation Request 22 22 1 CR23 Cancellation Request 23 23 1 CR24 Cancellation Request 24 24 1 CR25 Cancellation Request 25 25 1 CR26 Cancellation Request 26 26 1 CR27 Cancellation Request 27 27 1 CR28 Cancellation Request 28 28 1 CR29 Cancellation Request 29 29 1 CR30 Cancellation Request 30 30 1 CR31 Cancellation Request 31 31 1 TXBTO Tx Buffer Transmission Occurred 0xD8 32 read-only 0x00000000 TO0 Transmission Occurred 0 0 1 TO1 Transmission Occurred 1 1 1 TO2 Transmission Occurred 2 2 1 TO3 Transmission Occurred 3 3 1 TO4 Transmission Occurred 4 4 1 TO5 Transmission Occurred 5 5 1 TO6 Transmission Occurred 6 6 1 TO7 Transmission Occurred 7 7 1 TO8 Transmission Occurred 8 8 1 TO9 Transmission Occurred 9 9 1 TO10 Transmission Occurred 10 10 1 TO11 Transmission Occurred 11 11 1 TO12 Transmission Occurred 12 12 1 TO13 Transmission Occurred 13 13 1 TO14 Transmission Occurred 14 14 1 TO15 Transmission Occurred 15 15 1 TO16 Transmission Occurred 16 16 1 TO17 Transmission Occurred 17 17 1 TO18 Transmission Occurred 18 18 1 TO19 Transmission Occurred 19 19 1 TO20 Transmission Occurred 20 20 1 TO21 Transmission Occurred 21 21 1 TO22 Transmission Occurred 22 22 1 TO23 Transmission Occurred 23 23 1 TO24 Transmission Occurred 24 24 1 TO25 Transmission Occurred 25 25 1 TO26 Transmission Occurred 26 26 1 TO27 Transmission Occurred 27 27 1 TO28 Transmission Occurred 28 28 1 TO29 Transmission Occurred 29 29 1 TO30 Transmission Occurred 30 30 1 TO31 Transmission Occurred 31 31 1 TXBCF Tx Buffer Cancellation Finished 0xDC 32 read-only 0x00000000 CF0 Tx Buffer Cancellation Finished 0 0 1 CF1 Tx Buffer Cancellation Finished 1 1 1 CF2 Tx Buffer Cancellation Finished 2 2 1 CF3 Tx Buffer Cancellation Finished 3 3 1 CF4 Tx Buffer Cancellation Finished 4 4 1 CF5 Tx Buffer Cancellation Finished 5 5 1 CF6 Tx Buffer Cancellation Finished 6 6 1 CF7 Tx Buffer Cancellation Finished 7 7 1 CF8 Tx Buffer Cancellation Finished 8 8 1 CF9 Tx Buffer Cancellation Finished 9 9 1 CF10 Tx Buffer Cancellation Finished 10 10 1 CF11 Tx Buffer Cancellation Finished 11 11 1 CF12 Tx Buffer Cancellation Finished 12 12 1 CF13 Tx Buffer Cancellation Finished 13 13 1 CF14 Tx Buffer Cancellation Finished 14 14 1 CF15 Tx Buffer Cancellation Finished 15 15 1 CF16 Tx Buffer Cancellation Finished 16 16 1 CF17 Tx Buffer Cancellation Finished 17 17 1 CF18 Tx Buffer Cancellation Finished 18 18 1 CF19 Tx Buffer Cancellation Finished 19 19 1 CF20 Tx Buffer Cancellation Finished 20 20 1 CF21 Tx Buffer Cancellation Finished 21 21 1 CF22 Tx Buffer Cancellation Finished 22 22 1 CF23 Tx Buffer Cancellation Finished 23 23 1 CF24 Tx Buffer Cancellation Finished 24 24 1 CF25 Tx Buffer Cancellation Finished 25 25 1 CF26 Tx Buffer Cancellation Finished 26 26 1 CF27 Tx Buffer Cancellation Finished 27 27 1 CF28 Tx Buffer Cancellation Finished 28 28 1 CF29 Tx Buffer Cancellation Finished 29 29 1 CF30 Tx Buffer Cancellation Finished 30 30 1 CF31 Tx Buffer Cancellation Finished 31 31 1 TXBTIE Tx Buffer Transmission Interrupt Enable 0xE0 32 0x00000000 TIE0 Transmission Interrupt Enable 0 0 1 TIE1 Transmission Interrupt Enable 1 1 1 TIE2 Transmission Interrupt Enable 2 2 1 TIE3 Transmission Interrupt Enable 3 3 1 TIE4 Transmission Interrupt Enable 4 4 1 TIE5 Transmission Interrupt Enable 5 5 1 TIE6 Transmission Interrupt Enable 6 6 1 TIE7 Transmission Interrupt Enable 7 7 1 TIE8 Transmission Interrupt Enable 8 8 1 TIE9 Transmission Interrupt Enable 9 9 1 TIE10 Transmission Interrupt Enable 10 10 1 TIE11 Transmission Interrupt Enable 11 11 1 TIE12 Transmission Interrupt Enable 12 12 1 TIE13 Transmission Interrupt Enable 13 13 1 TIE14 Transmission Interrupt Enable 14 14 1 TIE15 Transmission Interrupt Enable 15 15 1 TIE16 Transmission Interrupt Enable 16 16 1 TIE17 Transmission Interrupt Enable 17 17 1 TIE18 Transmission Interrupt Enable 18 18 1 TIE19 Transmission Interrupt Enable 19 19 1 TIE20 Transmission Interrupt Enable 20 20 1 TIE21 Transmission Interrupt Enable 21 21 1 TIE22 Transmission Interrupt Enable 22 22 1 TIE23 Transmission Interrupt Enable 23 23 1 TIE24 Transmission Interrupt Enable 24 24 1 TIE25 Transmission Interrupt Enable 25 25 1 TIE26 Transmission Interrupt Enable 26 26 1 TIE27 Transmission Interrupt Enable 27 27 1 TIE28 Transmission Interrupt Enable 28 28 1 TIE29 Transmission Interrupt Enable 29 29 1 TIE30 Transmission Interrupt Enable 30 30 1 TIE31 Transmission Interrupt Enable 31 31 1 TXBCIE Tx Buffer Cancellation Finished Interrupt Enable 0xE4 32 0x00000000 CFIE0 Cancellation Finished Interrupt Enable 0 0 1 CFIE1 Cancellation Finished Interrupt Enable 1 1 1 CFIE2 Cancellation Finished Interrupt Enable 2 2 1 CFIE3 Cancellation Finished Interrupt Enable 3 3 1 CFIE4 Cancellation Finished Interrupt Enable 4 4 1 CFIE5 Cancellation Finished Interrupt Enable 5 5 1 CFIE6 Cancellation Finished Interrupt Enable 6 6 1 CFIE7 Cancellation Finished Interrupt Enable 7 7 1 CFIE8 Cancellation Finished Interrupt Enable 8 8 1 CFIE9 Cancellation Finished Interrupt Enable 9 9 1 CFIE10 Cancellation Finished Interrupt Enable 10 10 1 CFIE11 Cancellation Finished Interrupt Enable 11 11 1 CFIE12 Cancellation Finished Interrupt Enable 12 12 1 CFIE13 Cancellation Finished Interrupt Enable 13 13 1 CFIE14 Cancellation Finished Interrupt Enable 14 14 1 CFIE15 Cancellation Finished Interrupt Enable 15 15 1 CFIE16 Cancellation Finished Interrupt Enable 16 16 1 CFIE17 Cancellation Finished Interrupt Enable 17 17 1 CFIE18 Cancellation Finished Interrupt Enable 18 18 1 CFIE19 Cancellation Finished Interrupt Enable 19 19 1 CFIE20 Cancellation Finished Interrupt Enable 20 20 1 CFIE21 Cancellation Finished Interrupt Enable 21 21 1 CFIE22 Cancellation Finished Interrupt Enable 22 22 1 CFIE23 Cancellation Finished Interrupt Enable 23 23 1 CFIE24 Cancellation Finished Interrupt Enable 24 24 1 CFIE25 Cancellation Finished Interrupt Enable 25 25 1 CFIE26 Cancellation Finished Interrupt Enable 26 26 1 CFIE27 Cancellation Finished Interrupt Enable 27 27 1 CFIE28 Cancellation Finished Interrupt Enable 28 28 1 CFIE29 Cancellation Finished Interrupt Enable 29 29 1 CFIE30 Cancellation Finished Interrupt Enable 30 30 1 CFIE31 Cancellation Finished Interrupt Enable 31 31 1 TXEFC Tx Event FIFO Configuration 0xF0 32 0x00000000 EFSA Event FIFO Start Address 0 16 EFS Event FIFO Size 16 6 EFWM Event FIFO Watermark 24 6 TXEFS Tx Event FIFO Status 0xF4 32 read-only 0x00000000 EFFL Event FIFO Fill Level 0 6 EFGI Event FIFO Get Index 8 5 EFPI Event FIFO Put Index 16 5 EFF Event FIFO Full 24 1 TEFL Tx Event FIFO Element Lost 25 1 TXEFA Tx Event FIFO Acknowledge 0xF8 32 0x00000000 EFAI Event FIFO Acknowledge Index 0 5 CAN1 0x42002000 CAN1 16 CCL U22252.0.0 Configurable Custom Logic CCL CCL_ 0x42005C00 0 0x18 registers CTRL Control 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 2 1 SEQCTRL[%s] SEQ Control x 0x4 8 0x00 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 4 4 LUTCTRL[%s] LUT Control x 0x8 32 0x00000000 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 EDGESEL Edge Selection 7 1 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event in put source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM inout source 9 ALT2TC Alternate 2 TC input source 10 ASYNCEVENT ASYNC EVENT input source. The EVENT input will bypass edge detection logic. 11 INSEL1 Input Selection 1 12 4 INSEL2 Input Selection 2 16 4 INVEI Input Event Invert 20 1 LUTEI Event Input Enable 21 1 LUTEO Event Output Enable 22 1 TRUTH Truth Value 24 8 DAC U22142.0.1 Digital Analog Converter DAC DAC_ 0x42005400 0 0x15 registers DAC 28 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 CTRLB Control B 0x1 8 0x00 EOEN External Output Enable 0 1 IOEN Internal Output Enable 1 1 LEFTADJ Left Adjusted Data 2 1 VPD Voltage Pump Disable 3 1 DITHER Dither Enable 5 1 REFSEL Reference Selection 6 2 REFSELSelect INT1V Internal 1.0V reference 0 AVCC AVCC 1 VREFP External reference 2 EVCTRL Event Control 0x2 8 0x00 STARTEI Start Conversion Event Input 0 1 EMPTYEO Data Buffer Empty Event Output 1 1 INVEI Invert Event Input 2 1 INTENCLR Interrupt Enable Clear 0x4 8 0x00 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x5 8 0x00 UNDERRUN Underrun Interrupt Enable 0 1 EMPTY Data Buffer Empty Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 UNDERRUN Underrun 0 1 EMPTY Data Buffer Empty 1 1 STATUS Status 0x7 8 read-only 0x00 READY Ready 0 1 DATA Data 0x8 16 write-only 0x0000 DATA Data value to be converted 0 16 DATABUF Data Buffer 0xC 16 write-only 0x0000 DATABUF Data Buffer 0 16 SYNCBUSY Synchronization Busy 0x10 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 DATA Data 2 1 DATABUF Data Buffer 3 1 DBGCTRL Debug Control 0x14 8 0x00 DBGRUN Debug Run 0 1 DIVAS U22581.0.0 Divide and Square Root Accelerator DIVAS DIVAS_ 0x48000000 0 0x1C registers CTRLA Control 0x0 8 0x00 SIGNED Signed 0 1 DLZ Disable Leading Zero Optimization 1 1 STATUS Status 0x4 8 0x00 BUSY DIVAS Accelerator Busy 0 1 DBZ Writing a one to this bit clears DBZ to zero 1 1 DIVIDEND Dividend 0x8 32 0x00000000 DIVIDEND DIVIDEND 0 32 DIVISOR Divisor 0xC 32 0x00000000 DIVISOR DIVISOR 0 32 RESULT Result 0x10 32 read-only 0x00000000 RESULT RESULT 0 32 REM Remainder 0x14 32 read-only 0x00000000 REM REM 0 32 SQRNUM Square Root Input 0x18 32 0x00000000 SQRNUM Square Root Input 0 32 DMAC U22232.3.0 Direct Memory Access Controller DMAC DMAC_ 0x41006000 0 0x50 registers DMAC 7 CTRL Control 0x0 16 0x0000 SWRST Software Reset 0 1 DMAENABLE DMA Enable 1 1 CRCENABLE CRC Enable 2 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 CRCCTRL CRC Control 0x2 16 0x0000 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0x0 HWORD 16-bit bus transfer 0x1 WORD 32-bit bus transfer 0x2 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0x0 CRC32 CRC32 (IEEE 802.3) 0x1 CRCSRC CRC Input Source 8 6 CRCSRCSelect NOACT No action 0x00 IO I/O interface 0x01 CRCDATAIN CRC Data Input 0x4 32 0x00000000 CRCDATAIN CRC Data Input 0 32 CRCCHKSUM CRC Checksum 0x8 32 0x00000000 CRCCHKSUM CRC Checksum 0 32 CRCSTATUS CRC Status 0xC 8 0x00 CRCBUSY CRC Module Busy 0 1 CRCZERO CRC Zero 1 1 DBGCTRL Debug Control 0xD 8 0x00 DBGRUN Debug Run 0 1 QOSCTRL QOS Control 0xE 8 0x2A WRBQOS Write-Back Quality of Service 0 2 WRBQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 FQOS Fetch Quality of Service 2 2 FQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 DQOS Data Transfer Quality of Service 4 2 DQOSSelect DISABLE Background (no sensitive operation) 0x0 LOW Sensitive Bandwidth 0x1 MEDIUM Sensitive Latency 0x2 HIGH Critical Latency 0x3 SWTRIGCTRL Software Trigger Control 0x10 32 0x00000000 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 PRICTRL0 Priority Control 0 0x14 32 0x00000000 LVLPRI0 Level 0 Channel Priority Number 0 4 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 RRLVLEN0Select STATIC_LVL Static arbitration scheme for channels with level 3 priority 0x0 ROUND_ROBIN_LVL Round-robin arbitration scheme for channels with level 3 priority 0x1 LVLPRI1 Level 1 Channel Priority Number 8 4 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 LVLPRI2 Level 2 Channel Priority Number 16 4 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 LVLPRI3 Level 3 Channel Priority Number 24 4 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 INTPEND Interrupt Pending 0x20 16 0x0000 ID Channel ID 0 4 TERR Transfer Error 8 1 TCMPL Transfer Complete 9 1 SUSP Channel Suspend 10 1 FERR Fetch Error 13 1 BUSY Busy 14 1 PEND Pending 15 1 INTSTATUS Interrupt Status 0x24 32 read-only 0x00000000 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 CHINT8 Channel 8 Pending Interrupt 8 1 CHINT9 Channel 9 Pending Interrupt 9 1 CHINT10 Channel 10 Pending Interrupt 10 1 CHINT11 Channel 11 Pending Interrupt 11 1 BUSYCH Busy Channels 0x28 32 read-only 0x00000000 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 BUSYCH8 Busy Channel 8 8 1 BUSYCH9 Busy Channel 9 9 1 BUSYCH10 Busy Channel 10 10 1 BUSYCH11 Busy Channel 11 11 1 PENDCH Pending Channels 0x2C 32 read-only 0x00000000 PENDCH0 Pending Channel 0 0 1 PENDCH1 Pending Channel 1 1 1 PENDCH2 Pending Channel 2 2 1 PENDCH3 Pending Channel 3 3 1 PENDCH4 Pending Channel 4 4 1 PENDCH5 Pending Channel 5 5 1 PENDCH6 Pending Channel 6 6 1 PENDCH7 Pending Channel 7 7 1 PENDCH8 Pending Channel 8 8 1 PENDCH9 Pending Channel 9 9 1 PENDCH10 Pending Channel 10 10 1 PENDCH11 Pending Channel 11 11 1 ACTIVE Active Channel and Levels 0x30 32 read-only 0x00000000 LVLEX0 Level 0 Channel Trigger Request Executing 0 1 LVLEX1 Level 1 Channel Trigger Request Executing 1 1 LVLEX2 Level 2 Channel Trigger Request Executing 2 1 LVLEX3 Level 3 Channel Trigger Request Executing 3 1 ID Active Channel ID 8 5 ABUSY Active Channel Busy 15 1 BTCNT Active Channel Block Transfer Count 16 16 BASEADDR Descriptor Memory Section Base Address 0x34 32 0x00000000 BASEADDR Descriptor Memory Base Address 0 32 WRBADDR Write-Back Memory Section Base Address 0x38 32 0x00000000 WRBADDR Write-Back Memory Base Address 0 32 CHID Channel ID 0x3F 8 0x00 ID Channel ID 0 4 CHCTRLA Channel Control A 0x40 8 0x00 SWRST Channel Software Reset 0 1 ENABLE Channel Enable 1 1 RUNSTDBY Channel run in standby 6 1 CHCTRLB Channel Control B 0x44 32 0x00000000 EVACT Event Input Action 0 3 EVACTSelect NOACT No action 0x0 TRIG Transfer and periodic transfer trigger 0x1 CTRIG Conditional transfer trigger 0x2 CBLOCK Conditional block transfer 0x3 SUSPEND Channel suspend operation 0x4 RESUME Channel resume operation 0x5 SSKIP Skip next block suspend action 0x6 EVIE Channel Event Input Enable 3 1 EVOE Channel Event Output Enable 4 1 LVL Channel Arbitration Level 5 2 LVLSelect LVL0 Channel Priority Level 0 0x0 LVL1 Channel Priority Level 1 0x1 LVL2 Channel Priority Level 2 0x2 LVL3 Channel Priority Level 3 0x3 TRIGSRC Trigger Source 8 6 TRIGSRCSelect DISABLE Only software/event triggers 0x00 TSENS TSENS Result Ready Trigger 0x01 SERCOM0_RX SERCOM0 RX Trigger 0x02 SERCOM0_TX SERCOM0 TX Trigger 0x03 SERCOM1_RX SERCOM1 RX Trigger 0x04 SERCOM1_TX SERCOM1 TX Trigger 0x05 SERCOM2_RX SERCOM2 RX Trigger 0x06 SERCOM2_TX SERCOM2 TX Trigger 0x07 SERCOM3_RX SERCOM3 RX Trigger 0x08 SERCOM3_TX SERCOM3 TX Trigger 0x09 SERCOM4_RX SERCOM4 RX Trigger 0x0A SERCOM4_TX SERCOM4 TX Trigger 0x0B SERCOM5_RX SERCOM5 RX Trigger 0x0C SERCOM5_TX SERCOM5 TX Trigger 0x0D CAN0_DEBUG CAN0 Debug Trigger Reserved 0x0E CAN1_DEBUG CAN1 Debug Trigger Reserved 0x0F TCC0_OVF TCC0 Overflow Trigger 0x10 TCC0_MC0 TCC0 Match/Compare 0 Trigger 0x11 TCC0_MC1 TCC0 Match/Compare 1 Trigger 0x12 TCC0_MC2 TCC0 Match/Compare 2 Trigger 0x13 TCC0_MC3 TCC0 Match/Compare 3 Trigger 0x14 TCC1_OVF TCC1 Overflow Trigger 0x15 TCC1_MC0 TCC1 Match/Compare 0 Trigger 0x16 TCC1_MC1 TCC1 Match/Compare 1 Trigger 0x17 TCC2_OVF TCC2 Overflow Trigger 0x18 TCC2_MC0 TCC2 Match/Compare 0 Trigger 0x19 TCC2_MC1 TCC2 Match/Compare 1 Trigger 0x1A TC0_OVF TC0 Overflow Trigger 0x1B TC0_MC0 TC0 Match/Compare 0 Trigger 0x1C TC0_MC1 TC0 Match/Compare 1 Trigger 0x1D TC1_OVF TC1 Overflow Trigger 0x1E TC1_MC0 TC1 Match/Compare 0 Trigger 0x1F TC1_MC1 TC1 Match/Compare 1 Trigger 0x20 TC2_OVF TC2 Overflow Trigger 0x21 TC2_MC0 TC2 Match/Compare 0 Trigger 0x22 TC2_MC1 TC2 Match/Compare 1 Trigger 0x23 TC3_OVF TC3 Overflow Trigger 0x24 TC3_MC0 TC3 Match/Compare 0 Trigger 0x25 TC3_MC1 TC3 Match/Compare 1 Trigger 0x26 TC4_OVF TC4 Overflow Trigger 0x27 TC4_MC0 TC4 Match/Compare 0 Trigger 0x28 TC4_MC1 TC4 Match/Compare 1 Trigger 0x29 ADC0_RESRDY ADC0 Result Ready Trigger 0x2A ADC1_RESRDY ADC1 Result Ready Trigger 0x2B SDADC_RESRDY SDADC Result Ready Trigger 0x2C DAC_EMPTY DAC Empty Trigger 0x2D PTC_EOC PTC End of Conversion Trigger 0x2E PTC_WCOMP PTC Window Compare Trigger 0x2F PTC_SEQ PTC Sequence Trigger 0x30 SERCOM6_RX SERCOM6 RX Trigger 0x31 SERCOM6_TX SERCOM6 TX Trigger 0x32 SERCOM7_RX SERCOM7 RX Trigger 0x33 SERCOM7_TX SERCOM7 TX Trigger 0x34 TC5_OVF TC5 Overflow Trigger 0x35 TC5_MC0 TC5 Match/Compare 0 Trigger 0x36 TC5_MC1 TC5 Match/Compare 1 Trigger 0x37 TC6_OVF TC6 Overflow Trigger 0x38 TC6_MC0 TC6 Match/Compare 0 Trigger 0x39 TC6_MC1 TC6 Match/Compare 1 Trigger 0x3A TC7_OVF TC7 Overflow Trigger 0x3B TC7_MC0 TC7 Match/Compare 0 Trigger 0x3C TC7_MC1 TC7 Match/Compare 1 Trigger 0x3D TRIGACT Trigger Action 22 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0x0 BEAT One trigger required for each beat transfer 0x2 TRANSACTION One trigger required for each transaction 0x3 CMD Software Command 24 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHINTENCLR Channel Interrupt Enable Clear 0x4C 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTENSET Channel Interrupt Enable Set 0x4D 8 0x00 TERR Channel Transfer Error Interrupt Enable 0 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 SUSP Channel Suspend Interrupt Enable 2 1 CHINTFLAG Channel Interrupt Flag Status and Clear 0x4E 8 0x00 TERR Channel Transfer Error 0 1 TCMPL Channel Transfer Complete 1 1 SUSP Channel Suspend 2 1 CHSTATUS Channel Status 0x4F 8 read-only 0x00 PEND Channel Pending 0 1 BUSY Channel Busy 1 1 FERR Channel Fetch Error 2 1 DSU U22092.6.0 Device Service Unit DSU DSU_ 0x41002000 0 0x2000 registers CTRL Control 0x0 8 write-only 0x00 SWRST Software Reset 0 1 CRC 32-bit Cyclic Redundancy Code 2 1 MBIST Memory built-in self-test 3 1 CE Chip-Erase 4 1 ARR Auxiliary Row Read 6 1 SMSA Start Memory Stream Access 7 1 STATUSA Status A 0x1 8 0x00 DONE Done 0 1 CRSTEXT CPU Reset Phase Extension 1 1 BERR Bus Error 2 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only 0x00 PROT Protected 0 1 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 ADDR Address 0x4 32 0x00000000 AMOD Access Mode 0 2 ADDR Address 2 30 LENGTH Length 0x8 32 0x00000000 LENGTH Length 2 30 DATA Data 0xC 32 0x00000000 DATA Data 0 32 2 4 DCC[%s] Debug Communication Channel n 0x10 32 0x00000000 DATA Data 0 32 DID Device Identification 0x18 32 read-only 0x11011420 DEVSEL Device Select 0 8 REVISION Revision Number 8 4 DIE Die Number 12 4 SERIES Series 16 6 SERIESSelect 0 Cortex-M0+ processor, basic feature set 0 1 Cortex-M0+ processor, USB 1 FAMILY Family 23 5 FAMILYSelect 0 General purpose microcontroller 0 1 PicoPower 1 2 5V Industrial 2 PROCESSOR Processor 28 4 PROCESSORSelect 0 Cortex-M0 0 1 Cortex-M0+ 1 2 Cortex-M3 2 3 Cortex-M4 3 2 4 DCFG[%s] Device Configuration 0xF0 32 0x00000000 DCFG Device Configuration 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only 0x9F0FC002 EPRES Entry Present 0 1 FMT Format 1 1 ADDOFF Address Offset 12 20 ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only 0x00005002 END CoreSight ROM Table End 0x1008 32 read-only 0x00000000 END End Marker 0 32 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only 0x00000000 SMEMP System Memory Present 0 1 PID4 Peripheral Identification 4 0x1FD0 32 read-only 0x00000000 JEPCC JEP-106 Continuation Code 0 4 FKBC 4KB count 4 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only 0x00000000 PID6 Peripheral Identification 6 0x1FD8 32 read-only 0x00000000 PID7 Peripheral Identification 7 0x1FDC 32 read-only 0x00000000 PID0 Peripheral Identification 0 0x1FE0 32 read-only 0x000000D0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only 0x000000FC PARTNBH Part Number High 0 4 JEPIDCL Low part of the JEP-106 Identity Code 4 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only 0x00000009 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 REVISION Revision Number 4 4 PID3 Peripheral Identification 3 0x1FEC 32 read-only 0x00000000 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 CID0 Component Identification 0 0x1FF0 32 read-only 0x0000000D PREAMBLEB0 Preamble Byte 0 0 8 CID1 Component Identification 1 0x1FF4 32 read-only 0x00000010 PREAMBLE Preamble 0 4 CCLASS Component Class 4 4 CID2 Component Identification 2 0x1FF8 32 read-only 0x00000005 PREAMBLEB2 Preamble Byte 2 0 8 CID3 Component Identification 3 0x1FFC 32 read-only 0x000000B1 PREAMBLEB3 Preamble Byte 3 0 8 EIC U22543.0.0 External Interrupt Controller EIC EIC_ 0x40002800 0 0x3C registers EIC 3 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CKSEL Clock Selection 4 1 CKSELSelect CLK_GCLK Clocked by GCLK 0 CLK_ULP32K Clocked by ULP32K 1 NMICTRL Non-Maskable Interrupt Control 0x1 8 0x00 NMISENSE Non-Maskable Interrupt Sense Configuration 0 3 NMISENSESelect NONE No detection 0 RISE Rising-edge detection 1 FALL Falling-edge detection 2 BOTH Both-edges detection 3 HIGH High-level detection 4 LOW Low-level detection 5 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMIASYNCH Asynchronous Edge Detection Mode 4 1 NMIASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x2 16 0x0000 NMI Non-Maskable Interrupt 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy Status 0 1 ENABLE Enable Synchronization Busy Status 1 1 EVCTRL Event Control 0x8 32 0x00000000 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0xC 32 0x00000000 EXTINT External Interrupt Enable 0 16 INTENSET Interrupt Enable Set 0x10 32 0x00000000 EXTINT External Interrupt Enable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 0x00000000 EXTINT External Interrupt 0 16 ASYNCH External Interrupt Asynchronous Mode 0x18 32 0x00000000 ASYNCH Asynchronous Edge Detection Mode 0 16 ASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 2 4 CONFIG[%s] External Interrupt Sense Configuration 0x1C 32 0x00000000 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN0 Filter Enable 0 3 1 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN1 Filter Enable 1 7 1 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN2 Filter Enable 2 11 1 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN3 Filter Enable 3 15 1 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN4 Filter Enable 4 19 1 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN5 Filter Enable 5 23 1 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN6 Filter Enable 6 27 1 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 FILTEN7 Filter Enable 7 31 1 DEBOUNCEN Debouncer Enable 0x30 32 0x00000000 DEBOUNCEN Debouncer Enable 0 16 DPRESCALER Debouncer Prescaler 0x34 32 0x00000000 PRESCALER0 Debouncer Prescaler 0 3 PRESCALER0Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 STATES0 Debouncer number of states 3 1 STATES0Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 PRESCALER1 Debouncer Prescaler 4 3 PRESCALER1Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 STATES1 Debouncer number of states 7 1 STATES1Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 TICKON Pin Sampler frequency selection 16 1 TICKONSelect CLK_GCLK_EIC Clocked by GCLK 0 CLK_LFREQ Clocked by Low Frequency Clock 1 PINSTATE Pin State 0x38 32 read-only 0x00000000 PINSTATE Pin State 0 16 EVSYS U22561.1.0 Event System Interface EVSYS EVSYS_ 0x42000000 0 0x1C0 registers EVSYS 8 CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 CHSTATUS Channel Status 0xC 32 read-only 0x00000000 USRRDY0 Channel 0 User Ready 0 1 USRRDY1 Channel 1 User Ready 1 1 USRRDY2 Channel 2 User Ready 2 1 USRRDY3 Channel 3 User Ready 3 1 USRRDY4 Channel 4 User Ready 4 1 USRRDY5 Channel 5 User Ready 5 1 USRRDY6 Channel 6 User Ready 6 1 USRRDY7 Channel 7 User Ready 7 1 USRRDY8 Channel 8 User Ready 8 1 USRRDY9 Channel 9 User Ready 9 1 USRRDY10 Channel 10 User Ready 10 1 USRRDY11 Channel 11 User Ready 11 1 CHBUSY0 Channel 0 Busy 16 1 CHBUSY1 Channel 1 Busy 17 1 CHBUSY2 Channel 2 Busy 18 1 CHBUSY3 Channel 3 Busy 19 1 CHBUSY4 Channel 4 Busy 20 1 CHBUSY5 Channel 5 Busy 21 1 CHBUSY6 Channel 6 Busy 22 1 CHBUSY7 Channel 7 Busy 23 1 CHBUSY8 Channel 8 Busy 24 1 CHBUSY9 Channel 9 Busy 25 1 CHBUSY10 Channel 10 Busy 26 1 CHBUSY11 Channel 11 Busy 27 1 INTENCLR Interrupt Enable Clear 0x10 32 0x00000000 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTENSET Interrupt Enable Set 0x14 32 0x00000000 OVR0 Channel 0 Overrun Interrupt Enable 0 1 OVR1 Channel 1 Overrun Interrupt Enable 1 1 OVR2 Channel 2 Overrun Interrupt Enable 2 1 OVR3 Channel 3 Overrun Interrupt Enable 3 1 OVR4 Channel 4 Overrun Interrupt Enable 4 1 OVR5 Channel 5 Overrun Interrupt Enable 5 1 OVR6 Channel 6 Overrun Interrupt Enable 6 1 OVR7 Channel 7 Overrun Interrupt Enable 7 1 OVR8 Channel 8 Overrun Interrupt Enable 8 1 OVR9 Channel 9 Overrun Interrupt Enable 9 1 OVR10 Channel 10 Overrun Interrupt Enable 10 1 OVR11 Channel 11 Overrun Interrupt Enable 11 1 EVD0 Channel 0 Event Detection Interrupt Enable 16 1 EVD1 Channel 1 Event Detection Interrupt Enable 17 1 EVD2 Channel 2 Event Detection Interrupt Enable 18 1 EVD3 Channel 3 Event Detection Interrupt Enable 19 1 EVD4 Channel 4 Event Detection Interrupt Enable 20 1 EVD5 Channel 5 Event Detection Interrupt Enable 21 1 EVD6 Channel 6 Event Detection Interrupt Enable 22 1 EVD7 Channel 7 Event Detection Interrupt Enable 23 1 EVD8 Channel 8 Event Detection Interrupt Enable 24 1 EVD9 Channel 9 Event Detection Interrupt Enable 25 1 EVD10 Channel 10 Event Detection Interrupt Enable 26 1 EVD11 Channel 11 Event Detection Interrupt Enable 27 1 INTFLAG Interrupt Flag Status and Clear 0x18 32 0x00000000 OVR0 Channel 0 Overrun 0 1 OVR1 Channel 1 Overrun 1 1 OVR2 Channel 2 Overrun 2 1 OVR3 Channel 3 Overrun 3 1 OVR4 Channel 4 Overrun 4 1 OVR5 Channel 5 Overrun 5 1 OVR6 Channel 6 Overrun 6 1 OVR7 Channel 7 Overrun 7 1 OVR8 Channel 8 Overrun 8 1 OVR9 Channel 9 Overrun 9 1 OVR10 Channel 10 Overrun 10 1 OVR11 Channel 11 Overrun 11 1 EVD0 Channel 0 Event Detection 16 1 EVD1 Channel 1 Event Detection 17 1 EVD2 Channel 2 Event Detection 18 1 EVD3 Channel 3 Event Detection 19 1 EVD4 Channel 4 Event Detection 20 1 EVD5 Channel 5 Event Detection 21 1 EVD6 Channel 6 Event Detection 22 1 EVD7 Channel 7 Event Detection 23 1 EVD8 Channel 8 Event Detection 24 1 EVD9 Channel 9 Event Detection 25 1 EVD10 Channel 10 Event Detection 26 1 EVD11 Channel 11 Event Detection 27 1 SWEVT Software Event 0x1C 32 write-only 0x00000000 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 12 4 CHANNEL[%s] Channel n 0x20 32 0x00008000 EVGEN Event Generator Selection 0 7 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 RUNSTDBY Run in standby 14 1 ONDEMAND Generic Clock On Demand 15 1 50 4 USER[%s] User Multiplexer n 0x80 32 0x00000000 CHANNEL Channel Event Selection 0 5 FREQM U22572.0.0 Frequency Meter FREQM FREQM_ 0x40002C00 0 0x14 registers FREQM 4 CTRLA Control A Register 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 CTRLB Control B Register 0x1 8 write-only 0x00 START Start Measurement 0 1 CFGA Config A register 0x2 16 0x0000 REFNUM Number of Reference Clock Cycles 0 8 DIVREF Divide Reference Clock 15 1 INTENCLR Interrupt Enable Clear Register 0x8 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTENSET Interrupt Enable Set Register 0x9 8 0x00 DONE Measurement Done Interrupt Enable 0 1 INTFLAG Interrupt Flag Register 0xA 8 0x00 DONE Measurement Done 0 1 STATUS Status Register 0xB 8 0x00 BUSY FREQM Status 0 1 OVF Sticky Count Value Overflow 1 1 SYNCBUSY Synchronization Busy Register 0xC 32 read-only 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 VALUE Count Value Register 0x10 32 read-only 0x00000000 VALUE Measurement Value 0 24 GCLK U21221.1.1 Generic Clock Generator GCLK GCLK_ 0x40001C00 0 0x198 registers CTRLA Control 0x0 8 0x00 SWRST Software Reset 0 1 SYNCBUSY Synchronization Busy 0x4 32 read-only 0x00000000 SWRST Software Reset Synchroniation Busy bit 0 1 GENCTRL0 Generic Clock Generator Control 0 Synchronization Busy bits 2 1 GENCTRL0Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL1 Generic Clock Generator Control 1 Synchronization Busy bits 3 1 GENCTRL1Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL2 Generic Clock Generator Control 2 Synchronization Busy bits 4 1 GENCTRL2Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL3 Generic Clock Generator Control 3 Synchronization Busy bits 5 1 GENCTRL3Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL4 Generic Clock Generator Control 4 Synchronization Busy bits 6 1 GENCTRL4Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL5 Generic Clock Generator Control 5 Synchronization Busy bits 7 1 GENCTRL5Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL6 Generic Clock Generator Control 6 Synchronization Busy bits 8 1 GENCTRL6Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL7 Generic Clock Generator Control 7 Synchronization Busy bits 9 1 GENCTRL7Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 GENCTRL8 Generic Clock Generator Control 8 Synchronization Busy bits 10 1 GENCTRL8Select GCLK0 Generic clock generator 0 0x1 GCLK1 Generic clock generator 1 1 0x1 GCLK2 Generic clock generator 2 2 0x1 GCLK3 Generic clock generator 3 3 0x1 GCLK4 Generic clock generator 4 4 0x1 GCLK5 Generic clock generator 5 5 0x1 GCLK6 Generic clock generator 6 6 0x1 GCLK7 Generic clock generator 7 7 0x1 GCLK8 Generic clock generator 8 8 0x1 9 4 GENCTRL[%s] Generic Clock Generator Control 0x20 32 0x00000000 SRC Source Select 0 3 SRCSelect XOSC XOSC oscillator output 0 GCLKIN Generator input pad 1 GCLKGEN1 Generic clock generator 1 output 2 OSCULP32K OSCULP32K oscillator output 3 OSC32K OSC32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 OSC48M OSC48M oscillator output 6 DPLL96M DPLL96M output 7 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OOV Output Off Value 10 1 OE Output Enable 11 1 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 RUNSTDBY Run in Standby 13 1 DIV Division Factor 16 16 46 4 PCHCTRL[%s] Peripheral Clock Control 0x80 32 0x00000000 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 CHEN Channel Enable 6 1 WRTLOCK Write Lock 7 1 HMATRIXHS I76382.1.4 HSB Matrix HMATRIXB HMATRIXB_ 0x4100A000 0 0x168 registers 16 4 MCFG[%s] Master Configuration 0x0 32 0x00000002 ULBT Undefined Length Burst Type 0 3 ULBTSelect INFINITE Infinite Length 0 SINGLE Single Access 1 FOUR_BEAT Four Beat Burst 2 EIGHT_BEAT Eight Beat Burst 3 SIXTEEN_BEAT Sixteen Beat Burst 4 16 4 SCFG[%s] Slave Configuration 0x40 32 0x00000010 SLOT_CYCLE Maximum Number of Allowed Cycles for a Burst 0 8 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NO_DEFAULT No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. 0 LAST_DEFAULT Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. 1 FIXED_DEFAULT Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. 2 FIXED_DEFMSTR Fixed Index of Default Master 18 4 ARBT Arbitration Type 24 1 ARBTSelect ROUND_ROBIN Round-Robin Arbitration 0 FIXED_PRIORITY Fixed Priority Arbitration 1 4 0x8 PRS[%s] 0x080 PRAS Priority A for Slave 0x0 32 0x00000000 M0PR Master 0 Priority 0 4 M1PR Master 1 Priority 4 4 M2PR Master 2 Priority 8 4 M3PR Master 3 Priority 12 4 M4PR Master 4 Priority 16 4 M5PR Master 5 Priority 20 4 M6PR Master 6 Priority 24 4 M7PR Master 7 Priority 28 4 PRBS Priority B for Slave 0x4 32 0x00000000 M8PR Master 8 Priority 0 4 M9PR Master 9 Priority 4 4 M10PR Master 10 Priority 8 4 M11PR Master 11 Priority 12 4 M12PR Master 12 Priority 16 4 M13PR Master 13 Priority 20 4 M14PR Master 14 Priority 24 4 M15PR Master 15 Priority 28 4 MRCR Master Remap Control 0x100 32 0x00000000 RCB0 Remap Command Bit for Master 0 0 1 RCB0Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB1 Remap Command Bit for Master 1 1 1 RCB1Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB2 Remap Command Bit for Master 2 2 1 RCB2Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB3 Remap Command Bit for Master 3 3 1 RCB3Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB4 Remap Command Bit for Master 4 4 1 RCB4Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB5 Remap Command Bit for Master 5 5 1 RCB5Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB6 Remap Command Bit for Master 6 6 1 RCB6Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB7 Remap Command Bit for Master 7 7 1 RCB7Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB8 Remap Command Bit for Master 8 8 1 RCB8Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB9 Remap Command Bit for Master 9 9 1 RCB9Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB10 Remap Command Bit for Master 10 10 1 RCB10Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB11 Remap Command Bit for Master 11 11 1 RCB11Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB12 Remap Command Bit for Master 12 12 1 RCB12Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB13 Remap Command Bit for Master 13 13 1 RCB13Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB14 Remap Command Bit for Master 14 14 1 RCB14Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 RCB15 Remap Command Bit for Master 15 15 1 RCB15Select DIS Disable remapped address decoding for master 0 ENA Enable remapped address decoding for master 1 16 4 SFR[%s] Special Function 0x110 32 0x00000000 SFR Special Function Register 0 32 MCLK U22342.0.0 Main Clock MCLK MCLK_ 0x40000800 0 0x24 registers INTENCLR Interrupt Enable Clear 0x1 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 0x00 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 0x01 CKRDY Clock Ready 0 1 CPUDIV CPU Clock Division 0x4 8 0x01 CPUDIV CPU Clock Division Factor 0 8 CPUDIVSelect DIV1 Divide by 1 0x01 DIV2 Divide by 2 0x02 DIV4 Divide by 4 0x04 DIV8 Divide by 8 0x08 DIV16 Divide by 16 0x10 DIV32 Divide by 32 0x20 DIV64 Divide by 64 0x40 DIV128 Divide by 128 0x80 AHBMASK AHB Mask 0x10 32 0x00003CFF HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 DSU_ DSU AHB Clock Mask 3 1 HMATRIXHS_ HMATRIXHS AHB Clock Mask 4 1 NVMCTRL_ NVMCTRL AHB Clock Mask 5 1 HSRAM_ HSRAM AHB Clock Mask 6 1 DMAC_ DMAC AHB Clock Mask 7 1 CAN0_ CAN0 AHB Clock Mask 8 1 CAN1_ CAN1 AHB Clock Mask 9 1 PAC_ PAC AHB Clock Mask 10 1 NVMCTRL_PICACHU_ NVMCTRL_PICACHU AHB Clock Mask 11 1 DIVAS_ DIVAS AHB Clock Mask 12 1 HPB3_ HPB3 AHB Clock Mask 13 1 APBAMASK APBA Mask 0x14 32 0x00000FFF PAC_ PAC APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 MCLK_ MCLK APB Clock Enable 2 1 RSTC_ RSTC APB Clock Enable 3 1 OSCCTRL_ OSCCTRL APB Clock Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 5 1 SUPC_ SUPC APB Clock Enable 6 1 GCLK_ GCLK APB Clock Enable 7 1 WDT_ WDT APB Clock Enable 8 1 RTC_ RTC APB Clock Enable 9 1 EIC_ EIC APB Clock Enable 10 1 FREQM_ FREQM APB Clock Enable 11 1 TSENS_ TSENS APB Clock Enable 12 1 APBBMASK APBB Mask 0x18 32 0x00000007 PORT_ PORT APB Clock Enable 0 1 DSU_ DSU APB Clock Enable 1 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 HMATRIXHS_ HMATRIXHS APB Clock Enable 5 1 APBCMASK APBC Mask 0x1C 32 0x00000000 EVSYS_ EVSYS APB Clock Enable 0 1 SERCOM0_ SERCOM0 APB Clock Enable 1 1 SERCOM1_ SERCOM1 APB Clock Enable 2 1 SERCOM2_ SERCOM2 APB Clock Enable 3 1 SERCOM3_ SERCOM3 APB Clock Enable 4 1 SERCOM4_ SERCOM4 APB Clock Enable 5 1 SERCOM5_ SERCOM5 APB Clock Enable 6 1 TCC0_ TCC0 APB Clock Enable 9 1 TCC1_ TCC1 APB Clock Enable 10 1 TCC2_ TCC2 APB Clock Enable 11 1 TC0_ TC0 APB Clock Enable 12 1 TC1_ TC1 APB Clock Enable 13 1 TC2_ TC2 APB Clock Enable 14 1 TC3_ TC3 APB Clock Enable 15 1 TC4_ TC4 APB Clock Enable 16 1 ADC0_ ADC0 APB Clock Enable 17 1 ADC1_ ADC1 APB Clock Enable 18 1 SDADC_ SDADC APB Clock Enable 19 1 AC_ AC APB Clock Enable 20 1 DAC_ DAC APB Clock Enable 21 1 PTC_ PTC APB Clock Enable 22 1 CCL_ CCL APB Clock Enable 23 1 APBDMASK APBD Mask 0x20 32 0x00000000 SERCOM6_ SERCOM6 APB Clock Enable 0 1 SERCOM7_ SERCOM7 APB Clock Enable 1 1 TC5_ TC5 APB Clock Enable 2 1 TC6_ TC6 APB Clock Enable 3 1 TC7_ TC7 APB Clock Enable 4 1 MTB U20021.0.0 Cortex-M0+ Micro-Trace Buffer MTB MTB_ 0x41008000 0 0x1000 registers POSITION MTB Position 0x0 32 WRAP Pointer Value Wraps 2 1 POINTER Trace Packet Location Pointer 3 29 MASTER MTB Master 0x4 32 0x00000000 MASK Maximum Value of the Trace Buffer in SRAM 0 5 TSTARTEN Trace Start Input Enable 5 1 TSTOPEN Trace Stop Input Enable 6 1 SFRWPRIV Special Function Register Write Privilege 7 1 RAMPRIV SRAM Privilege 8 1 HALTREQ Halt Request 9 1 EN Main Trace Enable 31 1 FLOW MTB Flow 0x8 32 0x00000000 AUTOSTOP Auto Stop Tracing 0 1 AUTOHALT Auto Halt Request 1 1 WATERMARK Watermark value 3 29 BASE MTB Base 0xC 32 read-only ITCTRL MTB Integration Mode Control 0xF00 32 CLAIMSET MTB Claim Set 0xFA0 32 CLAIMCLR MTB Claim Clear 0xFA4 32 LOCKACCESS MTB Lock Access 0xFB0 32 LOCKSTATUS MTB Lock Status 0xFB4 32 read-only AUTHSTATUS MTB Authentication Status 0xFB8 32 read-only DEVARCH MTB Device Architecture 0xFBC 32 read-only DEVID MTB Device Configuration 0xFC8 32 read-only DEVTYPE MTB Device Type 0xFCC 32 read-only PID4 Peripheral Identification 4 0xFD0 32 read-only PID5 Peripheral Identification 5 0xFD4 32 read-only PID6 Peripheral Identification 6 0xFD8 32 read-only PID7 Peripheral Identification 7 0xFDC 32 read-only PID0 Peripheral Identification 0 0xFE0 32 read-only PID1 Peripheral Identification 1 0xFE4 32 read-only PID2 Peripheral Identification 2 0xFE8 32 read-only PID3 Peripheral Identification 3 0xFEC 32 read-only CID0 Component Identification 0 0xFF0 32 read-only CID1 Component Identification 1 0xFF4 32 read-only CID2 Component Identification 2 0xFF8 32 read-only CID3 Component Identification 3 0xFFC 32 read-only NVMCTRL U22074.0.2 Non-Volatile Memory Controller NVMCTRL NVMCTRL_ 0x41004000 0 0x30 registers NVMCTRL 6 CTRLA Control A 0x0 16 0x0000 CMD Command 0 7 CMDSelect ER Erase Row - Erases the row addressed by the ADDR register. 0x02 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x04 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x05 WAP Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. 0x06 SF Security Flow Command 0x0A WL Write lockbits 0x0F RWWEEER RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. 0x1A RWWEEWP RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. 0x1C LR Lock Region - Locks the region containing the address location in the ADDR register. 0x40 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 0x41 SPRM Sets the power reduction mode. 0x42 CPRM Clears the power reduction mode. 0x43 PBC Page Buffer Clear - Clears the page buffer. 0x44 SSB Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. 0x45 INVALL Invalidate all cache lines. 0x46 CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 0xA5 CTRLB Control B 0x4 32 0x00000080 RWS NVM Read Wait States 1 4 RWSSelect SINGLE Single Auto Wait State 0 HALF Half Auto Wait State 1 DUAL Dual Auto Wait State 2 MANW Manual Write 7 1 SLEEPPRM Power Reduction Mode during Sleep 8 2 SLEEPPRMSelect WAKEONACCESS NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. 0 WAKEUPINSTANT NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. 1 DISABLED Auto power reduction disabled. 3 READMODE NVMCTRL Read Mode 16 2 READMODESelect NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. 0x0 LOW_POWER Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. 0x1 DETERMINISTIC The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. 0x2 CACHEDIS Cache Disable 18 2 PARAM NVM Parameter 0x8 32 0x00000000 NVMP NVM Pages 0 16 PSZ Page Size 16 3 PSZSelect 8 8 bytes 0x0 16 16 bytes 0x1 32 32 bytes 0x2 64 64 bytes 0x3 128 128 bytes 0x4 256 256 bytes 0x5 512 512 bytes 0x6 1024 1024 bytes 0x7 RWWEEP RWW EEPROM Pages 20 12 INTENCLR Interrupt Enable Clear 0xC 8 0x00 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x10 8 0x00 READY NVM Ready Interrupt Enable 0 1 ERROR Error Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x14 8 0x00 READY NVM Ready 0 1 ERROR Error 1 1 STATUS Status 0x18 16 0x0000 PRM Power Reduction Mode 0 1 LOAD NVM Page Buffer Active Loading 1 1 PROGE Programming Error Status 2 1 LOCKE Lock Error Status 3 1 NVME NVM Error 4 1 SB Security Bit Status 8 1 ADDR Address 0x1C 32 0x00000000 ADDR NVM Address 0 22 LOCK Lock Section 0x20 16 0x0000 LOCK Region Lock Bits 0 16 PBLDATA0 Page Buffer Load Data 0 0x28 32 read-only 0x00000000 PBLDATA1 Page Buffer Load Data 1 0x2C 32 read-only 0x00000000 OSCCTRL U21192.1.0 Oscillators Control OSCCTRL OSCCTRL_ 0x40001000 0 0x3C registers INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 OSC48MRDY OSC48M Ready Interrupt Enable 4 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 8 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 9 1 DPLLLTO DPLL Time Out Interrupt Enable 10 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 11 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 XOSCRDY XOSC Ready Interrupt Enable 0 1 XOSCFAIL XOSC Clock Failure Detector Interrupt Enable 1 1 OSC48MRDY OSC48M Ready Interrupt Enable 4 1 DPLLLCKR DPLL Lock Rise Interrupt Enable 8 1 DPLLLCKF DPLL Lock Fall Interrupt Enable 9 1 DPLLLTO DPLL Time Out Interrupt Enable 10 1 DPLLLDRTO DPLL Ratio Ready Interrupt Enable 11 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 XOSCRDY XOSC Ready 0 1 XOSCFAIL XOSC Clock Failure Detector 1 1 OSC48MRDY OSC48M Ready 4 1 DPLLLCKR DPLL Lock Rise 8 1 DPLLLCKF DPLL Lock Fall 9 1 DPLLLTO DPLL Timeout 10 1 DPLLLDRTO DPLL Ratio Ready 11 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 XOSCRDY XOSC Ready 0 1 XOSCFAIL XOSC Clock Failure Detector 1 1 XOSCCKSW XOSC Clock Switch 2 1 OSC48MRDY OSC48M Ready 4 1 DPLLLCKR DPLL Lock Rise 8 1 DPLLLCKF DPLL Lock Fall 9 1 DPLLTO DPLL Timeout 10 1 DPLLLDRTO DPLL Ratio Ready 11 1 XOSCCTRL External Multipurpose Crystal Oscillator (XOSC) Control 0x10 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 CFDEN Xosc Clock Failure Detector Enable 3 1 SWBEN Xosc Clock Switch Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 GAIN Oscillator Gain 8 3 GAINSelect GAIN2 2 MHz 0 GAIN4 4 MHz 1 GAIN8 8 MHz 2 GAIN16 16 MHz 3 GAIN30 30 MHz 4 AMPGC Automatic Amplitude Gain Control 11 1 STARTUP Start-Up Time 12 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CFDPRESC Clock Failure Detector Prescaler 0x12 8 0x00 CFDPRESC Clock Failure Detector Prescaler 0 3 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 EVCTRL Event Control 0x13 8 0x00 CFDEO Clock Failure Detector Event Output Enable 0 1 OSC48MCTRL 48MHz Internal Oscillator (OSC48M) Control 0x14 8 0x82 ENABLE Oscillator Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 OSC48MDIV OSC48M Divider 0x15 8 0x0B DIV OSC48M Division Factor 0 4 DIVSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV3 16 MHz 2 DIV4 12 MHz 3 DIV5 9.6 MHz 4 DIV6 8 MHz 5 DIV7 6.86 MHz 6 DIV8 6 MHz 7 DIV9 5.33 MHz 8 DIV10 4.8 MHz 9 DIV11 4.36 MHz 10 DIV12 4 MHz 11 DIV13 3.69 MHz 12 DIV14 3.43 MHz 13 DIV15 3.2 MHz 14 DIV16 3 MHz 15 OSC48MSTUP OSC48M Startup Time 0x16 8 0x07 STARTUP Startup Time 0 3 STARTUPSelect CYCLE8 166 ns 0 CYCLE16 333 ns 1 CYCLE32 667 ns 2 CYCLE64 1.333 us 3 CYCLE128 2.667 us 4 CYCLE256 5.333 us 5 CYCLE512 10.667 us 6 CYCLE1024 21.333 us 7 OSC48MSYNCBUSY OSC48M Synchronization Busy 0x18 32 read-only 0x00000000 OSC48MDIV OSC48MDIV Synchronization Status 2 1 DPLLCTRLA DPLL Control 0x1C 8 0x80 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand 7 1 DPLLRATIO DPLL Ratio Control 0x20 32 0x00000000 LDR Loop Divider Ratio 0 12 LDRFRAC Loop Divider Ratio Fractional Part 16 4 DPLLCTRLB Digital Core Configuration 0x24 32 0x00000000 FILTER Proportional Integral Filter Selection 0 2 FILTERSelect DEFAULT Default filter mode 0 LBFILT Low bandwidth filter 1 HBFILT High bandwidth filter 2 HDFILT High damping filter 3 LPEN Low-Power Enable 2 1 WUF Wake Up Fast 3 1 REFCLK Reference Clock Selection 4 2 REFCLKSelect XOSC32K XOSC32K clock reference 0 XOSC XOSC clock reference 1 GCLK GCLK clock reference 2 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out. Automatic lock. 0 8MS Time-out if no lock within 8ms 4 9MS Time-out if no lock within 9ms 5 10MS Time-out if no lock within 10ms 6 11MS Time-out if no lock within 11ms 7 LBYPASS Lock Bypass 12 1 DIV Clock Divider 16 11 DPLLPRESC DPLL Prescaler 0x28 8 0x00 PRESC Output Clock Prescaler 0 2 PRESCSelect DIV1 DPLL output is divided by 1 0 DIV2 DPLL output is divided by 2 1 DIV4 DPLL output is divided by 4 2 DPLLSYNCBUSY DPLL Synchronization Busy 0x2C 8 read-only 0x00 ENABLE DPLL Enable Synchronization Status 1 1 DPLLRATIO DPLL Ratio Synchronization Status 2 1 DPLLPRESC DPLL Prescaler Synchronization Status 3 1 DPLLSTATUS DPLL Status 0x30 8 read-only 0x00 LOCK DPLL Lock Status 0 1 CLKRDY DPLL Clock Ready 1 1 CAL48M 48MHz Oscillator Calibration 0x38 32 0x00000000 FCAL Frequency Calibration (48MHz) 0 6 FRANGE Frequency Range (48MHz) 8 2 TCAL Temperature Calibration (48MHz) 16 6 OSC32KCTRL U22462.1.0 32k Oscillators Control OSC32KCTRL OSC32KCTRL_ 0x40001400 0 0x20 registers INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 OSC32KRDY OSC32K Ready Interrupt Enable 1 1 CLKFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 OSC32KRDY OSC32K Ready 1 1 CLKFAIL XOSC32K Clock Failure Detector 2 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 XOSC32KRDY XOSC32K Ready 0 1 OSC32KRDY OSC32K Ready 1 1 CLKFAIL XOSC32K Clock Failure Detector 2 1 CLKSW XOSC32K Clock switch 3 1 RTCCTRL Clock selection 0x10 32 0x00000000 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 1 OSC1K 1.024kHz from 32.768kHz internal oscillator 2 OSC32K 32.768kHz from 32.768kHz internal oscillator 3 XOSC1K 1.024kHz from 32.768kHz internal oscillator 4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 5 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 0x0080 ENABLE Oscillator Enable 1 1 XTALEN Crystal Oscillator Enable 2 1 EN32K 32kHz Output Enable 3 1 EN1K 1kHz Output Enable 4 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 STARTUPSelect CYCLE1 0.122 ms 0 CYCLE32 1.068 ms 1 CYCLE2048 62.6 ms 2 CYCLE4096 125 ms 3 CYCLE16384 500 ms 4 CYCLE32768 1000 ms 5 CYCLE65536 2000 ms 6 CYCLE131072 4000 ms 7 WRTLOCK Write Lock 12 1 CFDCTRL Clock Failure Detector Control 0x16 8 0x00 CFDEN Clock Failure Detector Enable 0 1 SWBACK Clock Switch Back 1 1 CFDPRESC Clock Failure Detector Prescaler 2 1 EVCTRL Event Control 0x17 8 0x00 CFDEO Clock Failure Detector Event Output Enable 0 1 OSC32K 32kHz Internal Oscillator (OSC32K) Control 0x18 32 0x003F0080 ENABLE Oscillator Enable 1 1 EN32K 32kHz Output Enable 2 1 EN1K 1kHz Output Enable 3 1 RUNSTDBY Run in Standby 6 1 ONDEMAND On Demand Control 7 1 STARTUP Oscillator Start-Up Time 8 3 STARTUPSelect CYCLE3 0.092 ms 0 CYCLE4 0.122 ms 1 CYCLE6 0.183 ms 2 CYCLE10 0.305 ms 3 CYCLE18 0.549 ms 4 CYCLE34 1.038 ms 5 CYCLE66 2.014 ms 6 CYCLE130 3.967 ms 7 WRTLOCK Write Lock 12 1 CALIB Oscillator Calibration 16 7 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 CALIB Oscillator Calibration 8 5 WRTLOCK Write Lock 15 1 PAC U21201.1.0 Peripheral Access Controller PAC PAC_ 0x40000000 0 0x44 registers WRCTRL Write control 0x0 32 0x00000000 PERID Peripheral identifier 0 16 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0 CLR Clear protection 1 SET Set protection 2 SETLCK Set and lock protection 3 EVCTRL Event control 0x4 8 0x00 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 0x00 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 0x00 ERR Peripheral access error interrupt enable 0 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 0x00000000 FLASH_ FLASH 0 1 HSRAMCM0P_ HSRAMCM0P 1 1 HSRAMDSU_ HSRAMDSU 2 1 HPB1_ HPB1 3 1 HPB0_ HPB0 4 1 HPB2_ HPB2 5 1 LPRAMDMAC_ LPRAMDMAC 6 1 DIVAS_ DIVAS 7 1 HPB3_ HPB3 8 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 0x00000000 PAC_ PAC 0 1 PM_ PM 1 1 MCLK_ MCLK 2 1 RSTC_ RSTC 3 1 OSCCTRL_ OSCCTRL 4 1 OSC32KCTRL_ OSC32KCTRL 5 1 SUPC_ SUPC 6 1 GCLK_ GCLK 7 1 WDT_ WDT 8 1 RTC_ RTC 9 1 EIC_ EIC 10 1 FREQM_ FREQM 11 1 TSENS_ TSENS 12 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 0x00000000 PORT_ PORT 0 1 DSU_ DSU 1 1 NVMCTRL_ NVMCTRL 2 1 DMAC_ DMAC 3 1 MTB_ MTB 4 1 HMATRIXHS_ HMATRIXHS 5 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 0x00000000 EVSYS_ EVSYS 0 1 SERCOM0_ SERCOM0 1 1 SERCOM1_ SERCOM1 2 1 SERCOM2_ SERCOM2 3 1 SERCOM3_ SERCOM3 4 1 SERCOM4_ SERCOM4 5 1 SERCOM5_ SERCOM5 6 1 CAN0_ CAN0 7 1 CAN1_ CAN1 8 1 TCC0_ TCC0 9 1 TCC1_ TCC1 10 1 TCC2_ TCC2 11 1 TC0_ TC0 12 1 TC1_ TC1 13 1 TC2_ TC2 14 1 TC3_ TC3 15 1 TC4_ TC4 16 1 ADC0_ ADC0 17 1 ADC1_ ADC1 18 1 SDADC_ SDADC 19 1 AC_ AC 20 1 DAC_ DAC 21 1 PTC_ PTC 22 1 CCL_ CCL 23 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 0x00000000 SERCOM6_ SERCOM6 0 1 SERCOM7_ SERCOM7 1 1 TC5_ TC5 2 1 TC6_ TC6 3 1 TC7_ TC7 4 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only 0x00000000 PAC_ PAC APB Protect Enable 0 1 PM_ PM APB Protect Enable 1 1 MCLK_ MCLK APB Protect Enable 2 1 RSTC_ RSTC APB Protect Enable 3 1 OSCCTRL_ OSCCTRL APB Protect Enable 4 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 5 1 SUPC_ SUPC APB Protect Enable 6 1 GCLK_ GCLK APB Protect Enable 7 1 WDT_ WDT APB Protect Enable 8 1 RTC_ RTC APB Protect Enable 9 1 EIC_ EIC APB Protect Enable 10 1 FREQM_ FREQM APB Protect Enable 11 1 TSENS_ TSENS APB Protect Enable 12 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only 0x00000002 PORT_ PORT APB Protect Enable 0 1 DSU_ DSU APB Protect Enable 1 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 DMAC_ DMAC APB Protect Enable 3 1 MTB_ MTB APB Protect Enable 4 1 HMATRIXHS_ HMATRIXHS APB Protect Enable 5 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only 0x02000000 EVSYS_ EVSYS APB Protect Enable 0 1 SERCOM0_ SERCOM0 APB Protect Enable 1 1 SERCOM1_ SERCOM1 APB Protect Enable 2 1 SERCOM2_ SERCOM2 APB Protect Enable 3 1 SERCOM3_ SERCOM3 APB Protect Enable 4 1 SERCOM4_ SERCOM4 APB Protect Enable 5 1 SERCOM5_ SERCOM5 APB Protect Enable 6 1 CAN0_ CAN0 APB Protect Enable 7 1 CAN1_ CAN1 APB Protect Enable 8 1 TCC0_ TCC0 APB Protect Enable 9 1 TCC1_ TCC1 APB Protect Enable 10 1 TCC2_ TCC2 APB Protect Enable 11 1 TC0_ TC0 APB Protect Enable 12 1 TC1_ TC1 APB Protect Enable 13 1 TC2_ TC2 APB Protect Enable 14 1 TC3_ TC3 APB Protect Enable 15 1 TC4_ TC4 APB Protect Enable 16 1 ADC0_ ADC0 APB Protect Enable 17 1 ADC1_ ADC1 APB Protect Enable 18 1 SDADC_ SDADC APB Protect Enable 19 1 AC_ AC APB Protect Enable 20 1 DAC_ DAC APB Protect Enable 21 1 PTC_ PTC APB Protect Enable 22 1 CCL_ CCL APB Protect Enable 23 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only 0x00000000 SERCOM6_ SERCOM6 APB Protect Enable 0 1 SERCOM7_ SERCOM7 APB Protect Enable 1 1 TC5_ TC5 APB Protect Enable 2 1 TC6_ TC6 APB Protect Enable 3 1 TC7_ TC7 APB Protect Enable 4 1 PM U22402.1.1 Power Manager PM PM_ 0x40000400 0 0xA registers SLEEPCFG Sleep Configuration 0x1 8 0x00 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE0 CPU clock is OFF 0 IDLE1 AHB clock is OFF 1 IDLE2 APB clock are OFF 2 STANDBY All Clocks are OFF 4 BACKUP Only Backup domain is powered ON 5 OFF All power domains are powered OFF 6 STDBYCFG Standby Configuration 0x8 16 0x0400 VREGSMOD Voltage Regulator Standby mode 6 2 VREGSMODSelect AUTO Automatic mode 0 PERFORMANCE Performance oriented 1 LP Low Power oriented 2 BBIASHS Back Bias for HMCRAMCHS 10 2 PORT U22102.1.1 Port Module PORT PORT_ 0x41000000 0 0x180 registers 3 0x80 GROUP[%s] 0x00 DIR Data Direction 0x0 32 0x00000000 DIRCLR Data Direction Clear 0x4 32 0x00000000 DIRSET Data Direction Set 0x8 32 0x00000000 DIRTGL Data Direction Toggle 0xC 32 0x00000000 OUT Data Output Value 0x10 32 0x00000000 OUTCLR Data Output Value Clear 0x14 32 0x00000000 OUTSET Data Output Value Set 0x18 32 0x00000000 OUTTGL Data Output Value Toggle 0x1C 32 0x00000000 IN Data Input Value 0x20 32 read-only 0x00000000 CTRL Control 0x24 32 0x00000000 SAMPLING Input Sampling Mode 0 32 WRCONFIG Write Configuration 0x28 32 write-only 0x00000000 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUXEN Select Peripheral Multiplexer 16 1 INEN Input Enable 17 1 PULLEN Pull Enable 18 1 DRVSTR Output Driver Strength Selection 22 1 PMUX Peripheral Multiplexing Template 24 4 WRPMUX Write PMUX Registers 28 1 WRPINCFG Write PINCFG Registers 30 1 HWSEL Half-Word Select 31 1 EVCTRL Event Input Control 0x2C 32 0x00000000 PID0 Port Event Pin Identifier 0 0 5 EVACT0 Port Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 PORTEI0 Port Event Enable Input 0 7 1 PID1 Port Event Pin Identifier 1 8 5 EVACT1 Port Event Action 1 13 2 PORTEI1 Port Event Enable Input 1 15 1 PID2 Port Event Pin Identifier 2 16 5 EVACT2 Port Event Action 2 21 2 PORTEI2 Port Event Enable Input 2 23 1 PID3 Port Event Pin Identifier 3 24 5 EVACT3 Port Event Action 3 29 2 PORTEI3 Port Event Enable Input 3 31 1 16 1 PMUX[%s] Peripheral Multiplexing n 0x30 8 0x00 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 32 1 PINCFG[%s] Pin Configuration n 0x40 8 0x00 PMUXEN Select Peripheral Multiplexer 0 1 INEN Input Enable 1 1 PULLEN Pull Enable 2 1 DRVSTR Output Driver Strength Selection 6 1 PORT_IOBUS PORT_IOBUS_ 0x60000000 PTC U22153.2.0 Peripheral Touch Controller PTC PTC_ 0x42005800 0 0x1 reserved PTC 30 RSTC U22392.0.2 Reset Controller RSTC RSTC_ 0x40000C00 0 0x1 registers RCAUSE Reset Cause 0x0 8 read-only POR Power On Reset 0 1 BODCORE Brown Out CORE Detector Reset 1 1 BODVDD Brown Out VDD Detector Reset 2 1 EXT External Reset 4 1 WDT Watchdog Reset 5 1 SYST System Reset Request 6 1 RTC U22501.1.1 Real-Time Counter RTC RTC_ 0x40002400 0 0x25 registers RTC 2 MODE0 32-bit Counter with Single 32-bit Compare RtcMode0 0x0 CTRLA MODE0 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0x0 COUNT16 Mode 1: 16-bit Counter 0x1 CLOCK Mode 2: Clock/Calendar 0x2 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB COUNTSYNC Count Read Synchronization Enable 15 1 EVCTRL MODE0 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE0 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE0 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE0 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE0 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 COMP0 COMP 0 Register Busy 5 1 COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE0 Counter Value 0x18 32 0x00000000 COUNT Counter Value 0 32 COMP MODE0 Compare n Value 0x20 32 0x00000000 COMP Compare Value 0 32 MODE1 16-bit Counter with Two 16-bit Compares MODE0 RtcMode1 0x0 CTRLA MODE1 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB COUNTSYNC Count Read Synchronization Enable 15 1 EVCTRL MODE1 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE1 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE1 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE1 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE1 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 COUNT COUNT Register Busy 3 1 PER PER Register Busy 4 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COUNTSYNC Count Read Synchronization Enable Bit Busy 15 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 COUNT MODE1 Counter Value 0x18 16 0x0000 COUNT Counter Value 0 16 PER MODE1 Counter Period 0x1C 16 0x0000 PER Counter Period 0 16 2 2 COMP[%s] MODE1 Compare n Value 0x20 16 0x0000 COMP Compare Value 0 16 MODE2 Clock/Calendar with Alarm MODE0 RtcMode2 0x0 CTRLA MODE2 Control A 0x0 16 0x0000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 CLKREP Clock Representation 6 1 MATCHCLR Clear on Match 7 1 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB CLOCKSYNC Clock Read Synchronization Enable 15 1 EVCTRL MODE2 Event Control 0x4 32 0x00000000 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 ALARMEO0 Alarm 0 Event Output Enable 8 1 OVFEO Overflow Event Output Enable 15 1 INTENCLR MODE2 Interrupt Enable Clear 0x8 16 0x0000 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTENSET MODE2 Interrupt Enable Set 0xA 16 0x0000 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 ALARM0 Alarm 0 Interrupt Enable 8 1 OVF Overflow Interrupt Enable 15 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0xC 16 0x0000 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 ALARM0 Alarm 0 8 1 OVF Overflow 15 1 DBGCTRL Debug Control 0xE 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only 0x00000000 SWRST Software Reset Bit Busy 0 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 CLOCK CLOCK Register Busy 3 1 ALARM0 ALARM 0 Register Busy 5 1 MASK0 MASK 0 Register Busy 11 1 CLOCKSYNC Clock Read Synchronization Enable Bit Busy 15 1 FREQCORR Frequency Correction 0x14 8 0x00 VALUE Correction Value 0 7 SIGN Correction Sign 7 1 CLOCK MODE2 Clock Value 0x18 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 ALARM MODE2_ALARM Alarm n Value 0x20 32 0x00000000 SECOND Second 0 6 MINUTE Minute 6 6 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 DAY Day 17 5 MONTH Month 22 4 YEAR Year 26 6 MASK MODE2_ALARM Alarm n Mask 0x24 8 0x00 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 SDADC U22601.0.1 Sigma-Delta Analog Digital Converter SDADC SDADC_ 0x42004C00 0 0x2F registers SDADC 29 CTRLA Control A 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Control 7 1 REFCTRL Reference Control 0x1 8 0x00 REFSEL Reference Selection 0 2 REFSELSelect INTREF Internal Bandgap Reference 0 AREFB External Reference 1 DAC Internal DAC Output 2 INTVCC VDDANA 3 REFRANGE Reference Range 4 2 ONREFBUF Reference Buffer 7 1 CTRLB Control B 0x2 16 0x2000 PRESCALER Prescaler Configuration 0 8 PRESCALERSelect DIV2 Peripheral clock divided by 2 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 OSR Over Sampling Ratio 8 3 OSRSelect OSR64 Over Sampling Ratio is 64 0x0 OSR128 Over Sampling Ratio is 128 0x1 OSR256 Over Sampling Ratio is 256 0x2 OSR512 Over Sampling Ratio is 512 0x3 OSR1024 Over Sampling Ratio is 1024 0x4 SKPCNT Skip Sample Count 12 4 EVCTRL Event Control 0x4 8 0x00 FLUSHEI Flush Event Input Enable 0 1 STARTEI Start Conversion Event Input Enable 1 1 FLUSHINV Flush Event Invert Enable 2 1 STARTINV Satrt Event Invert Enable 3 1 RESRDYEO Result Ready Event Out 4 1 WINMONEO Window Monitor Event Out 5 1 INTENCLR Interrupt Enable Clear 0x5 8 0x00 RESRDY Result Ready Interrupt Disable 0 1 OVERRUN Overrun Interrupt Disable 1 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x6 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x7 8 0x00 RESRDY Result Ready Interrupt Flag 0 1 OVERRUN Overrun Interrupt Flag 1 1 WINMON Window Monitor Interrupt Flag 2 1 SEQSTATUS Sequence Status 0x8 8 read-only 0x00 SEQSTATE Sequence State 0 4 SEQBUSY Sequence Busy 7 1 INPUTCTRL Input Control 0x9 8 0x00 MUXSEL SDADC Input Selection 0 4 MUXSELSelect AIN0 SDADC AIN0 Pin 0x0 AIN1 SDADC AIN1 Pin 0x1 AIN2 SDADC AIN2 Pin 0x2 CTRLC Control C 0xA 8 0x00 FREERUN Free Running Mode 0 1 WINCTRL Window Monitor Control 0xB 8 0x00 WINMODE Window Monitor Mode 0 3 WINLT Window Monitor Lower Threshold 0xC 32 0x00000000 WINLT Window Lower Threshold 0 24 WINUT Window Monitor Upper Threshold 0x10 32 0x00000000 WINUT Window Upper Threshold 0 24 OFFSETCORR Offset Correction 0x14 32 0x00000000 OFFSETCORR Offset Correction Value 0 24 GAINCORR Gain Correction 0x18 16 0x0001 GAINCORR Gain Correction Value 0 14 SHIFTCORR Shift Correction 0x1A 8 0x00 SHIFTCORR Shift Correction Value 0 4 SWTRIG Software Trigger 0x1C 8 0x00 FLUSH SDADC Flush 0 1 START Start SDADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x20 32 read-only 0x00000000 SWRST SWRST Synchronization Busy 0 1 ENABLE ENABLE Synchronization Busy 1 1 CTRLC CTRLC Synchronization Busy 2 1 INPUTCTRL INPUTCTRL Synchronization Busy 3 1 WINCTRL WINCTRL Synchronization Busy 4 1 WINLT WINLT Synchronization Busy 5 1 WINUT WINUT Synchronization Busy 6 1 OFFSETCORR OFFSETCTRL Synchronization Busy 7 1 GAINCORR GAINCORR Synchronization Busy 8 1 SHIFTCORR SHIFTCORR Synchronization Busy 9 1 SWTRIG SWTRG Synchronization Busy 10 1 ANACTRL ANACTRL Synchronization Busy 11 1 RESULT Result 0x24 32 read-only 0x00000000 RESULT Result Value 0 24 RESERVED 24 8 SEQCTRL Sequence Control 0x28 8 0x00 SEQEN Enable Positive Input in the Sequence 0 3 ANACTRL Analog Control 0x2C 8 0x00 CTRSDADC SDADC Control 0 6 ONCHOP Chopper 6 1 BUFTEST BUFTEST 7 1 DBGCTRL Debug Control 0x2E 8 0x00 DBGRUN Debug Run 0 1 SERCOM0 U22013.2.0 Serial Communication Interface SERCOM SERCOM_ 0x42000400 0 0x31 registers I2CM I2C Master Mode SercomI2cm 0x0 CTRLA I2CM Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run in Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 MEXTTOEN Master SCL Low Extend Timeout 22 1 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SCLSM SCL Clock Stretch Mode 27 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CM Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 QCEN Quick Command Enable 9 1 CMD Command 16 2 ACKACT Acknowledge Action 18 1 BAUD I2CM Baud Rate 0xC 32 0x00000000 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 INTENCLR I2CM Interrupt Enable Clear 0x14 8 0x00 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CM Interrupt Enable Set 0x16 8 0x00 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CM Interrupt Flag Status and Clear 0x18 8 0x00 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 ERROR Combined Error Interrupt 7 1 STATUS I2CM Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 ARBLOST Arbitration Lost 1 1 RXNACK Received Not Acknowledge 2 1 BUSSTATE Bus State 4 2 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 LENERR Length Error 10 1 SYNCBUSY I2CM Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 SYSOP System Operation Synchronization Busy 2 1 ADDR I2CM Address 0x24 32 0x00000000 ADDR Address Value 0 11 LENEN Length Enable 13 1 HS High Speed Mode 14 1 TENBITEN Ten Bit Addressing Enable 15 1 LEN Length 16 8 DATA I2CM Data 0x28 8 0x00 DATA Data Value 0 8 DBGCTRL I2CM Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 I2CS I2C Slave Mode I2CM SercomI2cs 0x0 CTRLA I2CS Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 PINOUT Pin Usage 16 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SCLSM SCL Clock Stretch Mode 27 1 LOWTOUTEN SCL Low Timeout Enable 30 1 CTRLB I2CS Control B 0x4 32 0x00000000 SMEN Smart Mode Enable 8 1 GCMD PMBus Group Command 9 1 AACKEN Automatic Address Acknowledge 10 1 AMODE Address Mode 14 2 CMD Command 16 2 ACKACT Acknowledge Action 18 1 INTENCLR I2CS Interrupt Enable Clear 0x14 8 0x00 PREC Stop Received Interrupt Disable 0 1 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET I2CS Interrupt Enable Set 0x16 8 0x00 PREC Stop Received Interrupt Enable 0 1 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG I2CS Interrupt Flag Status and Clear 0x18 8 0x00 PREC Stop Received Interrupt 0 1 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 STATUS I2CS Status 0x1A 16 0x0000 BUSERR Bus Error 0 1 COLL Transmit Collision 1 1 RXNACK Received Not Acknowledge 2 1 DIR Read/Write Direction 3 1 SR Repeated Start 4 1 LOWTOUT SCL Low Timeout 6 1 CLKHOLD Clock Hold 7 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 HS High Speed 10 1 SYNCBUSY I2CS Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 ADDR I2CS Address 0x24 32 0x00000000 GENCEN General Call Address Enable 0 1 ADDR Address Value 1 10 TENBITEN Ten Bit Addressing Enable 15 1 ADDRMASK Address Mask 17 10 DATA I2CS Data 0x28 8 0x00 DATA Data Value 0 8 SPIS SPI Slave Mode I2CM SercomSpis 0x0 CTRLA SPIS Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0x0 IDLE_HIGH SCK is high when idle 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0x0 LSB LSB is transferred first 0x1 CTRLB SPIS Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0x0 9_BIT 9 bits 0x1 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 RXEN Receiver Enable 17 1 BAUD SPIS Baud Rate 0xC 8 0x00 BAUD Baud Rate Value 0 8 INTENCLR SPIS Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPIS Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPIS Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPIS Status 0x1A 16 0x0000 BUFOVF Buffer Overflow 2 1 SYNCBUSY SPIS Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 ADDR SPIS Address 0x24 32 0x00000000 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPIS Data 0x28 32 0x00000000 DATA Data Value 0 9 DBGCTRL SPIS Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 SPIM SPI Master Mode I2CM SercomSpim 0x0 CTRLA SPIM Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1] 0x1 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 PAD3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] 0x3 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] 0x0 PAD1 SERCOM PAD[1] 0x1 PAD2 SERCOM PAD[2] 0x2 PAD3 SERCOM PAD[3] 0x3 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0x0 IDLE_HIGH SCK is high when idle 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0x0 LSB LSB is transferred first 0x1 CTRLB SPIM Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0x0 9_BIT 9 bits 0x1 PLOADEN Data Preload Enable 6 1 SSDE Slave Select Low Detect Enable 9 1 MSSEN Master Slave Select Enable 13 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 RXEN Receiver Enable 17 1 BAUD SPIM Baud Rate 0xC 8 0x00 BAUD Baud Rate Value 0 8 INTENCLR SPIM Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET SPIM Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG SPIM Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 ERROR Combined Error Interrupt 7 1 STATUS SPIM Status 0x1A 16 0x0000 BUFOVF Buffer Overflow 2 1 SYNCBUSY SPIM Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 ADDR SPIM Address 0x24 32 0x00000000 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 DATA SPIM Data 0x28 32 0x00000000 DATA Data Value 0 9 DBGCTRL SPIM Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 USART_EXT USART EXTERNAL CLOCK Mode I2CM SercomUsart_ext 0x0 CTRLA USART_EXT Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0x0 PAD2 SERCOM PAD[2] is used for data transmission 0x1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 CTRLB USART_EXT Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 LINCMD LIN Command 24 2 CTRLC USART_EXT Control C 0x8 32 0x00000000 GTIME RS485 Guard Time 0 3 BRKLEN LIN Master Break Length 8 2 HDRDLY LIN Master Header Delay 10 2 BAUD USART_EXT Baud Rate 0xC 16 0x0000 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_EXT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 16 RXPL USART_EXT Receive Pulse Length 0xE 8 0x00 RXPL Receive Pulse Length 0 8 INTENCLR USART_EXT Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART_EXT Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART_EXT Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART_EXT Status 0x1A 16 0x0000 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_EXT Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 DATA USART_EXT Data 0x28 16 0x0000 DATA Data Value 0 9 DBGCTRL USART_EXT Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 USART_INT USART INTERNAL CLOCK Mode I2CM SercomUsart_int 0x0 CTRLA USART_INT Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 RUNSTDBY Run during Standby 7 1 IBON Immediate Buffer Overflow Notification 8 1 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0x0 PAD2 SERCOM PAD[2] is used for data transmission 0x1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 CTRLB USART_INT Control B 0x4 32 0x00000000 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 COLDEN Collision Detection Enable 8 1 SFDE Start of Frame Detection Enable 9 1 ENC Encoding Format 10 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 TXEN Transmitter Enable 16 1 RXEN Receiver Enable 17 1 LINCMD LIN Command 24 2 CTRLC USART_INT Control C 0x8 32 0x00000000 GTIME RS485 Guard Time 0 3 BRKLEN LIN Master Break Length 8 2 HDRDLY LIN Master Header Delay 10 2 BAUD USART_INT Baud Rate 0xC 16 0x0000 BAUD Baud Rate Value 0 16 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 0x0000 BAUD Baud Rate Value 0 16 RXPL USART_INT Receive Pulse Length 0xE 8 0x00 RXPL Receive Pulse Length 0 8 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 0x00 DRE Data Register Empty Interrupt Disable 0 1 TXC Transmit Complete Interrupt Disable 1 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 RXBRK Break Received Interrupt Disable 5 1 ERROR Combined Error Interrupt Disable 7 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 0x00 DRE Data Register Empty Interrupt Enable 0 1 TXC Transmit Complete Interrupt Enable 1 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 RXBRK Break Received Interrupt Enable 5 1 ERROR Combined Error Interrupt Enable 7 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 0x00 DRE Data Register Empty Interrupt 0 1 TXC Transmit Complete Interrupt 1 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 CTSIC Clear To Send Input Change Interrupt 4 1 RXBRK Break Received Interrupt 5 1 ERROR Combined Error Interrupt 7 1 STATUS USART_INT Status 0x1A 16 0x0000 PERR Parity Error 0 1 FERR Frame Error 1 1 BUFOVF Buffer Overflow 2 1 CTS Clear To Send 3 1 ISF Inconsistent Sync Field 4 1 COLL Collision Detected 5 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only 0x00000000 SWRST Software Reset Synchronization Busy 0 1 ENABLE SERCOM Enable Synchronization Busy 1 1 CTRLB CTRLB Synchronization Busy 2 1 DATA USART_INT Data 0x28 16 0x0000 DATA Data Value 0 9 DBGCTRL USART_INT Debug Control 0x30 8 0x00 DBGSTOP Debug Mode 0 1 SERCOM1 0x42000800 SERCOM2 0x42000C00 SERCOM2 11 SERCOM3 0x42001000 SERCOM3 12 SERCOM4 0x42001400 SERCOM4 13 SERCOM5 0x42001800 SERCOM5 14 SERCOM6 0x43000000 SERCOM7 0x43000400 SUPC U21172.2.0 Supply Controller SUPC SUPC_ 0x40001800 0 0x24 registers INTENCLR Interrupt Enable Clear 0x0 32 0x00000000 BODVDDRDY BODVDD Ready 0 1 BODVDDDET BODVDD Detection 1 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 INTENSET Interrupt Enable Set 0x4 32 0x00000000 BODVDDRDY BODVDD Ready 0 1 BODVDDDET BODVDD Detection 1 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 0x00000000 BODVDDRDY BODVDD Ready 0 1 BODVDDDET BODVDD Detection 1 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 STATUS Power and Clocks Status 0xC 32 read-only 0x00000000 BODVDDRDY BODVDD Ready 0 1 BODVDDDET BODVDD Detection 1 1 BVDDSRDY BODVDD Synchronization Ready 2 1 VREG33RDY VREG33 Ready 6 1 BODVDD BODVDD Control 0x10 32 0x00000000 ENABLE Enable 1 1 HYST Hysteresis Enable 2 1 ACTION Action when Threshold Crossed 3 2 ACTIONSelect NONE No action 0x0 RESET The BODVDD generates a reset 0x1 INT The BODVDD generates an interrupt 0x2 STDBYCFG Configuration in Standby mode 5 1 RUNSTDBY Run during Standby 6 1 ACTCFG Configuration in Active mode 8 1 PSEL Prescaler Select 12 4 PSELSelect DIV2 Divide clock by 2 0x0 DIV4 Divide clock by 4 0x1 DIV8 Divide clock by 8 0x2 DIV16 Divide clock by 16 0x3 DIV32 Divide clock by 32 0x4 DIV64 Divide clock by 64 0x5 DIV128 Divide clock by 128 0x6 DIV256 Divide clock by 256 0x7 DIV512 Divide clock by 512 0x8 DIV1024 Divide clock by 1024 0x9 DIV2048 Divide clock by 2048 0xA DIV4096 Divide clock by 4096 0xB DIV8192 Divide clock by 8192 0xC DIV16384 Divide clock by 16384 0xD DIV32768 Divide clock by 32768 0xE DIV65536 Divide clock by 65536 0xF LEVEL Threshold Level for VDD 16 6 VREG VREG Control 0x18 32 0x00000000 ENABLE Enable 1 1 RUNSTDBY Run during Standby 6 1 VREF VREF Control 0x1C 32 0x00000000 TSEN Temperature Sensor Output Enable 1 1 VREFOE Voltage Reference Output Enable 2 1 RUNSTDBY Run during Standby 6 1 ONDEMAND On Demand Control 7 1 SEL Voltage Reference Selection 16 4 SELSelect 1V024 1.024V voltage reference typical value 0x0 2V048 2.048V voltage reference typical value 0x2 4V096 4.096V voltage reference typical value 0x3 VREG33 VREG33 Control 0x20 32 0x00000010 ENABLE VREG33 Enable 1 1 ENRDY VREG33 Ready Enable 2 1 BYPASS VREG33 Bypass 3 1 ISOEN Isolation Enable 4 1 TC0 U22493.0.0 Basic Timer Counter TC TC_ 0x42003000 0 0x38 registers COUNT8 8-bit Counter Mode TcCount8 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT8 Count 0x14 8 0x00 COUNT Counter Value 0 8 PER COUNT8 Period 0x1B 8 0xFF PER Period Value 0 8 2 1 CC[%s] COUNT8 Compare and Capture 0x1C 8 0x00 CC Counter/Compare Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 0xFF PERBUF Period Buffer Value 0 8 2 1 CCBUF[%s] COUNT8 Compare and Capture Buffer 0x30 8 0x00 CCBUF Counter/Compare Buffer Value 0 8 COUNT16 16-bit Counter Mode COUNT8 TcCount16 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT16 Count 0x14 16 0x0000 COUNT Counter Value 0 16 2 2 CC[%s] COUNT16 Compare and Capture 0x1C 16 0x0000 CC Counter/Compare Value 0 16 2 2 CCBUF[%s] COUNT16 Compare and Capture Buffer 0x30 16 0x0000 CCBUF Counter/Compare Buffer Value 0 16 COUNT32 32-bit Counter Mode COUNT8 TcCount32 0x0 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 EVCTRL Event Control 0x6 16 0x0000 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 TCINV TC Event Input Polarity 4 1 TCEI TC Event Enable 5 1 OVFEO Event Output Enable 8 1 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 INTENCLR Interrupt Enable Clear 0x8 8 0x00 OVF OVF Interrupt Disable 0 1 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 INTENSET Interrupt Enable Set 0x9 8 0x00 OVF OVF Interrupt Enable 0 1 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 0x00 OVF OVF Interrupt Flag 0 1 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 STATUS Status 0xB 8 0x01 STOP Stop Status Flag 0 1 SLAVE Slave Status Flag 1 1 PERBUFV Synchronization Busy Status 3 1 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 WAVE Waveform Generation Control 0xC 8 0x00 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 DRVCTRL Control C 0xD 8 0x00 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 DBGCTRL Debug Control 0xF 8 0x00 DBGRUN Run During Debug 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only 0x00000000 SWRST swrst 0 1 ENABLE enable 1 1 CTRLB CTRLB 2 1 STATUS STATUS 3 1 COUNT Counter 4 1 PER Period 5 1 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT COUNT32 Count 0x14 32 0x00000000 COUNT Counter Value 0 32 2 4 CC[%s] COUNT32 Compare and Capture 0x1C 32 0x00000000 CC Counter/Compare Value 0 32 2 4 CCBUF[%s] COUNT32 Compare and Capture Buffer 0x30 32 0x00000000 CCBUF Counter/Compare Buffer Value 0 32 TC1 0x42003400 TC2 0x42003800 TC3 0x42003C00 TC3 23 TC4 0x42004000 TC4 24 TC5 0x43000800 TC6 0x43000C00 TC7 0x43001000 TCC0 U22133.1.0 Timer Counter Control TCC TCC_ 0x42002400 0 0x80 registers TCC0 17 CTRLA Control A 0x0 32 0x00000000 SWRST Software Reset 0 1 ENABLE Enable 1 1 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 RUNSTDBY Run in Standby 11 1 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 ALOCK Auto Lock 14 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 DMAOS DMA One-shot Trigger Mode 23 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CTRLBCLR Control B Clear 0x4 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 CTRLBSET Control B Set 0x5 8 0x00 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 SWRST Swrst Busy 0 1 ENABLE Enable Busy 1 1 CTRLB Ctrlb Busy 2 1 STATUS Status Busy 3 1 COUNT Count Busy 4 1 PATT Pattern Busy 5 1 WAVE Wave Busy 6 1 PER Period Busy 7 1 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 FCTRLA Recoverable Fault A Configuration 0xC 32 0x00000000 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 RESTART Fault A Restart 7 1 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 FILTERVAL Fault A Filter Value 24 4 FCTRLB Recoverable Fault B Configuration 0x10 32 0x00000000 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 RESTART Fault B Restart 7 1 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 FILTERVAL Fault B Filter Value 24 4 WEXCTRL Waveform Extension Configuration 0x14 32 0x00000000 OTMX Output Matrix 0 2 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 DTHS Dead-time High Side Outputs Value 24 8 DRVCTRL Driver Control 0x18 32 0x00000000 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 DBGCTRL Debug Control 0x1E 8 0x00 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 EVCTRL Event Control 0x20 32 0x00000000 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 OVFEO Overflow/Underflow Output Event Enable 8 1 TRGEO Retrigger Output Event Enable 9 1 CNTEO Timer/counter Output Event Enable 10 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 INTENCLR Interrupt Enable Clear 0x24 32 0x00000000 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTENSET Interrupt Enable Set 0x28 32 0x00000000 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 CNT Counter Interrupt Enable 2 1 ERR Error Interrupt Enable 3 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 0x00000000 OVF Overflow 0 1 TRG Retrigger 1 1 CNT Counter 2 1 ERR Error 3 1 UFS Non-Recoverable Update Fault 10 1 DFS Non-Recoverable Debug Fault 11 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 STATUS Status 0x30 32 0x00000001 STOP Stop 0 1 IDX Ramp 1 1 UFS Non-recoverable Update Fault State 2 1 DFS Non-Recoverable Debug Fault State 3 1 SLAVE Slave 4 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTBIN Recoverable Fault B Input 9 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTB Recoverable Fault B State 13 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT1 Non-Recoverable Fault 1 State 15 1 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 COUNT Count 0x34 32 0x00000000 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 0x00000000 COUNT Counter Value 6 18 PATT Pattern 0x38 16 0x0000 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 WAVE Waveform Control 0x3C 32 0x00000000 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 CIPEREN Circular period Enable 7 1 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 PER Period 0x40 32 0xFFFFFFFF PER Period Value 0 24 PER_DITH4_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 0xFFFFFFFF DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 4 4 CC[%s] Compare and Capture 0x44 32 0x00000000 CC Channel Compare/Capture Value 0 24 4 4 CC_DITH4_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 4 CC Channel Compare/Capture Value 4 20 4 4 CC_DITH5_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 5 CC Channel Compare/Capture Value 5 19 4 4 CC_DITH6_MODE[%s] Compare and Capture CC[%s] 0x44 32 0x00000000 DITHER Dithering Cycle Number 0 6 CC Channel Compare/Capture Value 6 18 PATTBUF Pattern Buffer 0x64 16 0x0000 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PERBUF Period Buffer 0x6C 32 0xFFFFFFFF PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 0xFFFFFFFF DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 4 4 CCBUF[%s] Compare and Capture Buffer 0x70 32 0x00000000 CCBUF Channel Compare/Capture Buffer Value 0 24 4 4 CCBUF_DITH4_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 4 4 CCBUF_DITH5_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF Channel Compare/Capture Buffer Value 5 19 4 4 CCBUF_DITH6_MODE[%s] Compare and Capture Buffer CCBUF[%s] 0x70 32 0x00000000 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF Channel Compare/Capture Buffer Value 6 18 TCC1 0x42002800 TCC1 18 TCC2 0x42002C00 TCC2 19 TSENS U22611.0.1 Temperature Sensor TSENS TSENS_ 0x40003000 0 0x25 registers TSENS 5 CTRLA Control A Register 0x0 8 0x00 SWRST Software Reset 0 1 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 CTRLB Control B Register 0x1 8 write-only 0x00 START Start Measurement 0 1 CTRLC Control C Register 0x2 8 0x00 WINMODE Window Monitor Mode 0 3 WINMODESelect DISABLE No window mode (default) 0 ABOVE VALUE greater than WINLT 1 BELOW VALUE less than WINUT 2 INSIDE VALUE greater than WINLT and VALUE less than WINUT 3 OUTSIDE VALUE less than WINLT or VALUE greater than WINUT 4 HYST_ABOVE VALUE greater than WINUT with hysteresis to WINLT 5 HYST_BELOW VALUE less than WINLST with hysteresis to WINUT 6 FREERUN Free Running Measurement 4 1 EVCTRL Event Control Register 0x3 8 0x00 STARTEI Start Conversion Event Input Enable 0 1 STARTINV Start Conversion Event Invert Enable 1 1 WINEO Window Monitor Event Out 2 1 INTENCLR Interrupt Enable Clear Register 0x4 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 OVF Overflow Interrupt Enable 3 1 INTENSET Interrupt Enable Set Register 0x5 8 0x00 RESRDY Result Ready Interrupt Enable 0 1 OVERRUN Overrun Interrupt Enable 1 1 WINMON Window Monitor Interrupt Enable 2 1 OVF Overflow Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear Register 0x6 8 0x00 RESRDY Result Ready 0 1 OVERRUN Overrun 1 1 WINMON Window Monitor 2 1 OVF Overflow 3 1 STATUS Status Register 0x7 8 read-only 0x00 OVF Result Overflow 0 1 SYNCBUSY Synchronization Busy Register 0x8 32 read-only 0x00000000 SWRST Software Reset Busy 0 1 ENABLE Enable Busy 1 1 VALUE Value Register 0xC 32 read-only 0x00000000 VALUE Measurement Value 0 24 WINLT Window Monitor Lower Threshold Register 0x10 32 0x00000000 WINLT Window Lower Threshold 0 24 WINUT Window Monitor Upper Threshold Register 0x14 32 0x00000000 WINUT Window Upper Threshold 0 24 GAIN Gain Register 0x18 32 0x00000000 GAIN Time Amplifier Gain 0 24 OFFSET Offset Register 0x1C 32 0x00000000 OFFSETC Offset Correction 0 24 CAL Calibration Register 0x20 32 0x00000000 FCAL Frequency Calibration 0 6 TCAL Temperature Calibration 8 6 DBGCTRL Debug Control Register 0x24 8 0x00 DBGRUN Debug Run 0 1 WDT U22511.0.1 Watchdog Timer WDT WDT_ 0x40002000 0 0xD registers WDT 1 CTRLA Control 0x0 8 0x00 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 ALWAYSON Always-On 7 1 CONFIG Configuration 0x1 8 0xBB PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB EWCTRL Early Warning Interrupt Control 0x2 8 0x0B EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0x0 CYC16 16 clock cycles 0x1 CYC32 32 clock cycles 0x2 CYC64 64 clock cycles 0x3 CYC128 128 clock cycles 0x4 CYC256 256 clock cycles 0x5 CYC512 512 clock cycles 0x6 CYC1024 1024 clock cycles 0x7 CYC2048 2048 clock cycles 0x8 CYC4096 4096 clock cycles 0x9 CYC8192 8192 clock cycles 0xA CYC16384 16384 clock cycles 0xB INTENCLR Interrupt Enable Clear 0x4 8 0x00 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 0x00 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 0x00 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only 0x00000000 ENABLE Enable Busy 1 1 WEN Window Enable Busy 2 1 ALWAYSON Always-On Busy 3 1 CLEAR Clear Busy 4 1 CLEAR Clear 0xC 8 write-only 0x00 CLEAR Watchdog Clear 0 8 CLEARSelect KEY Clear Key 0xA5 MPU Memory Protection Unit MPU MPU_ 0xE000ED90 0 0x14 registers TYPE MPU Type Register 0x0 32 read-only SEPARATE Separate instruction and Data Memory MapsRegions 0 1 DREGION Number of Data Regions 8 8 IREGION Number of Instruction Regions 16 8 CTRL MPU Control Register 0x4 32 ENABLE MPU Enable 0 1 HFNMIENA Enable Hard Fault and NMI handlers 1 1 PRIVDEFENA Enables privileged software access to default memory map 2 1 RNR MPU Region Number Register 0x8 32 REGION Region referenced by RBAR and RASR 0 8 RBAR MPU Region Base Address Register 0xC 32 REGION Region number 0 4 VALID Region number valid 4 1 ADDR Region base address 5 27 RASR MPU Region Attribute and Size Register 0x10 32 ENABLE Region Enable 0 1 SIZE Region Size 1 5 SRD Sub-region disable 8 8 B Bufferable bit 16 1 C Cacheable bit 17 1 S Shareable bit 18 1 TEX TEX bit 19 3 AP Access Permission 24 3 XN Execute Never Attribute 28 1 NVIC Nested Vectored Interrupt Controller NVIC NVIC_ 0xE000E100 0 0x320 registers ISER Interrupt Set Enable Register 0x0 32 0x00000000 SETENA Interrupt set enable bits 0 31 ICER Interrupt Clear Enable Register 0x80 32 0x00000000 CLRENA Interrupt clear-enable bits 0 31 ISPR Interrupt Set Pending Register 0x100 32 0x00000000 SETPEND Interrupt set-pending bits 0 31 ICPR Interrupt Clear Pending Register 0x180 32 0x00000000 CLRPEND Interrupt clear-pending bits 0 31 8 4 IPR[%s] Interrupt Priority Register n 0x300 32 0x00000000 PRI0 Priority of interrupt n 0 2 PRI1 Priority of interrupt n 8 2 PRI2 Priority of interrupt n 16 2 PRI3 Priority of interrupt n 24 2 SysTick System timer SysTick SysTick_ 0xE000E010 0 0x10 registers CSR SysTick Control and Status Register 0x0 32 0x4 ENABLE SysTick Counter Enable 0 1 ENABLESelect VALUE_0 Counter disabled 0 VALUE_1 Counter enabled 1 TICKINT SysTick Exception Request Enable 1 1 TICKINTSelect VALUE_0 Counting down to 0 does not assert the SysTick exception request 0 VALUE_1 Counting down to 0 asserts the SysTick exception request 1 CLKSOURCE Clock Source 0=external, 1=processor 2 1 CLKSOURCESelect VALUE_0 External clock 0 VALUE_1 Processor clock 1 COUNTFLAG Timer counted to 0 since last read of register 16 1 RVR SysTick Reload Value Register 0x4 32 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 CVR SysTick Current Value Register 0x8 32 CURRENT Current value at the time the register is accessed 0 24 CALIB SysTick Calibration Value Register 0xC 32 read-only 0 TENMS Reload value to use for 10ms timing 0 24 SKEW TENMS is rounded from non-integer ratio 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 NOREF No Separate Reference Clock 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SystemControl System Control Registers SystemControl SystemControl_ 0xE000E000 0 0xD34 registers CPUID CPUID Base Register 0xD00 32 read-only 0x410CC601 REVISION Minor revision number 0 4 PARTNO Processor Part Number, 0xC60=Cortex-M0+ 4 12 ARCHITECTURE Processor Architecture, 0xC=ARMv6-M 16 4 VARIANT Major revision number 20 4 IMPLEMENTER Implementer code, ARM=0x41 24 8 ICSR Interrupt Control and State Register 0xD04 32 0x00000000 VECTACTIVE Debug: Exception number of currently executing exception, or 0 if thread mode 0 9 VECTPENDING Exception number of the highest priority pending enabled exception 12 9 ISRPENDING Debug: NVIC interrupt pending 22 1 ISRPREEMPT Debug: Pending exception serviced on exit from debug halt 23 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the SysTick exception 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSTSETSelect VALUE_0 Write: no effect; read: SysTick exception is not pending 0 VALUE_1 Write: changes SysTick exception state to pending; read: SysTick exception is pending 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the PendSV exception 1 PENDSVSET PendSV set-pending bit 28 1 PENDSVSETSelect VALUE_0 Write: no effect; read: PendSV exception is not pending 0 VALUE_1 Write: changes PendSV exception state to pending; read: PendSV exception is pending 1 NMIPENDSET NMI set-pending bit 31 1 NMIPENDSETSelect VALUE_0 Write: no effect; read: NMI exception is not pending 0 VALUE_1 Write: changes NMI exception state to pending; read: NMI exception is pending 1 VTOR Vector Table Offset Register 0xD08 32 0x00000000 TBLOFF Vector table base offset 7 25 AIRCR Application Interrupt and Reset Control Register 0xD0C 32 0x00000000 VECTCLRACTIVE Debug: Clear state information 1 1 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 No system reset request 0 VALUE_1 Asserts a signal to the outer system that requests a reset 1 ENDIANNESS Data Endianness, 0=little, 1=big 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 VECTKEY Register key (0x05FA) 16 16 SCR System Control Register 0xD10 32 0x00000000 SLEEPONEXIT Sleep-On-Exit when exiting Handler mode 1 1 SLEEPONEXITSelect VALUE_0 O not sleep when returning to Thread mode 0 VALUE_1 Enter sleep, or deep sleep, on return from an ISR 1 SLEEPDEEP Uses Deep Sleep as low power mode 2 1 SLEEPDEEPSelect VALUE_0 Sleep 0 VALUE_1 Deep sleep 1 SEVONPEND Send Event on Pending bit 4 1 SEVONPENDSelect VALUE_0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 CCR Configuration and Control Register 0xD14 32 read-only 0x00000204 UNALIGN_TRP Unaligned accesses generates a Hard Fault 3 1 UNALIGN_TRPSelect VALUE_0 Do not trap unaligned halfword and word accesses 0 VALUE_1 Trap unaligned halfword and word accesses 1 STKALIGN Stack 8-byte aligned on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 SHPR2 System Handler Priority Register 2 0xD1C 32 0x00000000 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0xD20 32 0x00000000 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 SHCSR System Handler Control and State Register 0xD24 32 0x00000000 SVCALLPENDED 15 1 DFSR Debug Fault Status Register 0xD30 32 0x00000000 HALTED Halt request debug event active 0 1 BKPT Breakpoint debug event 1 1 DWTTRAP DWT debug event 2 1 VCATCH Vector catch debug event 3 1 EXTERNAL EDBGRQ debug event 4 1