#[doc = "Register `OSC48MCTRL` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `OSC48MCTRL` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `ENABLE` reader - Oscillator Enable"] pub struct ENABLE_R(crate::FieldReader); impl ENABLE_R { pub(crate) fn new(bits: bool) -> Self { ENABLE_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for ENABLE_R { type Target = crate::FieldReader; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `ENABLE` writer - Oscillator Enable"] pub struct ENABLE_W<'a> { w: &'a mut W, } impl<'a> ENABLE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); self.w } } #[doc = "Field `RUNSTDBY` reader - Run in Standby"] pub struct RUNSTDBY_R(crate::FieldReader); impl RUNSTDBY_R { pub(crate) fn new(bits: bool) -> Self { RUNSTDBY_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for RUNSTDBY_R { type Target = crate::FieldReader; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `RUNSTDBY` writer - Run in Standby"] pub struct RUNSTDBY_W<'a> { w: &'a mut W, } impl<'a> RUNSTDBY_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); self.w } } #[doc = "Field `ONDEMAND` reader - On Demand Control"] pub struct ONDEMAND_R(crate::FieldReader); impl ONDEMAND_R { pub(crate) fn new(bits: bool) -> Self { ONDEMAND_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for ONDEMAND_R { type Target = crate::FieldReader; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `ONDEMAND` writer - On Demand Control"] pub struct ONDEMAND_W<'a> { w: &'a mut W, } impl<'a> ONDEMAND_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); self.w } } impl R { #[doc = "Bit 1 - Oscillator Enable"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 6 - Run in Standby"] #[inline(always)] pub fn runstdby(&self) -> RUNSTDBY_R { RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - On Demand Control"] #[inline(always)] pub fn ondemand(&self) -> ONDEMAND_R { ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) } } impl W { #[doc = "Bit 1 - Oscillator Enable"] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } #[doc = "Bit 6 - Run in Standby"] #[inline(always)] pub fn runstdby(&mut self) -> RUNSTDBY_W { RUNSTDBY_W { w: self } } #[doc = "Bit 7 - On Demand Control"] #[inline(always)] pub fn ondemand(&mut self) -> ONDEMAND_W { ONDEMAND_W { w: self } } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { self.0.bits(bits); self } } #[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] pub struct OSC48MCTRL_SPEC; impl crate::RegisterSpec for OSC48MCTRL_SPEC { type Ux = u8; } #[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] impl crate::Readable for OSC48MCTRL_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] impl crate::Writable for OSC48MCTRL_SPEC { type Writer = W; } #[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] impl crate::Resettable for OSC48MCTRL_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0x82 } }