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| author | Arne Dußin | 2021-11-06 11:50:33 +0100 |
|---|---|---|
| committer | Arne Dußin | 2021-11-06 11:50:33 +0100 |
| commit | 0666a6ba1dbd66cf8b93c113e362ccbcd99152a0 (patch) | |
| tree | a184284dbd2316f4624f092e4e7521ea8c90855b /src/gclk.rs | |
| download | samc21-0666a6ba1dbd66cf8b93c113e362ccbcd99152a0.tar.gz samc21-0666a6ba1dbd66cf8b93c113e362ccbcd99152a0.zip | |
Initial commit
Diffstat (limited to 'src/gclk.rs')
| -rw-r--r-- | src/gclk.rs | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/gclk.rs b/src/gclk.rs new file mode 100644 index 0000000..b91b638 --- /dev/null +++ b/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: crate::Reg<ctrla::CTRLA_SPEC>, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: crate::Reg<syncbusy::SYNCBUSY_SPEC>, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x44 - Generic Clock Generator Control"] + pub genctrl: [crate::Reg<genctrl::GENCTRL_SPEC>; 9], + _reserved3: [u8; 0x3c], + #[doc = "0x80..0x138 - Peripheral Clock Control"] + pub pchctrl: [crate::Reg<pchctrl::PCHCTRL_SPEC>; 46], +} +#[doc = "CTRLA register accessor: an alias for `Reg<CTRLA_SPEC>`"] +pub type CTRLA = crate::Reg<ctrla::CTRLA_SPEC>; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY register accessor: an alias for `Reg<SYNCBUSY_SPEC>`"] +pub type SYNCBUSY = crate::Reg<syncbusy::SYNCBUSY_SPEC>; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL register accessor: an alias for `Reg<GENCTRL_SPEC>`"] +pub type GENCTRL = crate::Reg<genctrl::GENCTRL_SPEC>; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL register accessor: an alias for `Reg<PCHCTRL_SPEC>`"] +pub type PCHCTRL = crate::Reg<pchctrl::PCHCTRL_SPEC>; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; |
