Initial commit

1 files changed, 164 insertions, 0 deletions

diff --git a/src/oscctrl/dpllpresc.rs b/src/oscctrl/dpllpresc.rs
new file mode 100644
index 0000000..8dcc427
--- /dev/null
+++ b/src/oscctrl/dpllpresc.rs
@@ -0,0 +1,164 @@
+#[doc = "Register `DPLLPRESC` reader"]
+pub struct R(crate::R<DPLLPRESC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DPLLPRESC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DPLLPRESC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DPLLPRESC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DPLLPRESC` writer"]
+pub struct W(crate::W<DPLLPRESC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DPLLPRESC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DPLLPRESC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DPLLPRESC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Output Clock Prescaler\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PRESC_A {
+    #[doc = "0: DPLL output is divided by 1"]
+    DIV1 = 0,
+    #[doc = "1: DPLL output is divided by 2"]
+    DIV2 = 1,
+    #[doc = "2: DPLL output is divided by 4"]
+    DIV4 = 2,
+}
+impl From<PRESC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PRESC_A) -> Self {
+        variant as _
+    }
+}
+#[doc = "Field `PRESC` reader - Output Clock Prescaler"]
+pub struct PRESC_R(crate::FieldReader<u8, PRESC_A>);
+impl PRESC_R {
+    pub(crate) fn new(bits: u8) -> Self {
+        PRESC_R(crate::FieldReader::new(bits))
+    }
+    #[doc = r"Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PRESC_A> {
+        match self.bits {
+            0 => Some(PRESC_A::DIV1),
+            1 => Some(PRESC_A::DIV2),
+            2 => Some(PRESC_A::DIV4),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIV1`"]
+    #[inline(always)]
+    pub fn is_div1(&self) -> bool {
+        **self == PRESC_A::DIV1
+    }
+    #[doc = "Checks if the value of the field is `DIV2`"]
+    #[inline(always)]
+    pub fn is_div2(&self) -> bool {
+        **self == PRESC_A::DIV2
+    }
+    #[doc = "Checks if the value of the field is `DIV4`"]
+    #[inline(always)]
+    pub fn is_div4(&self) -> bool {
+        **self == PRESC_A::DIV4
+    }
+}
+impl core::ops::Deref for PRESC_R {
+    type Target = crate::FieldReader<u8, PRESC_A>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PRESC` writer - Output Clock Prescaler"]
+pub struct PRESC_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PRESC_W<'a> {
+    #[doc = r"Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: PRESC_A) -> &'a mut W {
+        unsafe { self.bits(variant.into()) }
+    }
+    #[doc = "DPLL output is divided by 1"]
+    #[inline(always)]
+    pub fn div1(self) -> &'a mut W {
+        self.variant(PRESC_A::DIV1)
+    }
+    #[doc = "DPLL output is divided by 2"]
+    #[inline(always)]
+    pub fn div2(self) -> &'a mut W {
+        self.variant(PRESC_A::DIV2)
+    }
+    #[doc = "DPLL output is divided by 4"]
+    #[inline(always)]
+    pub fn div4(self) -> &'a mut W {
+        self.variant(PRESC_A::DIV4)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Output Clock Prescaler"]
+    #[inline(always)]
+    pub fn presc(&self) -> PRESC_R {
+        PRESC_R::new((self.bits & 0x03) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Output Clock Prescaler"]
+    #[inline(always)]
+    pub fn presc(&mut self) -> PRESC_W {
+        PRESC_W { w: self }
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"]
+pub struct DPLLPRESC_SPEC;
+impl crate::RegisterSpec for DPLLPRESC_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"]
+impl crate::Readable for DPLLPRESC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"]
+impl crate::Writable for DPLLPRESC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DPLLPRESC to value 0"]
+impl crate::Resettable for DPLLPRESC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}