diff options
| author | Arne Dußin | 2021-11-06 11:50:33 +0100 |
|---|---|---|
| committer | Arne Dußin | 2021-11-06 11:50:33 +0100 |
| commit | 0666a6ba1dbd66cf8b93c113e362ccbcd99152a0 (patch) | |
| tree | a184284dbd2316f4624f092e4e7521ea8c90855b /src/tc0/count8/intenset.rs | |
| download | samc21-0666a6ba1dbd66cf8b93c113e362ccbcd99152a0.tar.gz samc21-0666a6ba1dbd66cf8b93c113e362ccbcd99152a0.zip | |
Initial commit
Diffstat (limited to 'src/tc0/count8/intenset.rs')
| -rw-r--r-- | src/tc0/count8/intenset.rs | 250 |
1 files changed, 250 insertions, 0 deletions
diff --git a/src/tc0/count8/intenset.rs b/src/tc0/count8/intenset.rs new file mode 100644 index 0000000..8a5ab3b --- /dev/null +++ b/src/tc0/count8/intenset.rs @@ -0,0 +1,250 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R<INTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W<INTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub struct OVF_R(crate::FieldReader<bool, bool>); +impl OVF_R { + pub(crate) fn new(bits: bool) -> Self { + OVF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OVF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub struct OVF_W<'a> { + w: &'a mut W, +} +impl<'a> OVF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub struct ERR_R(crate::FieldReader<bool, bool>); +impl ERR_R { + pub(crate) fn new(bits: bool) -> Self { + ERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub struct ERR_W<'a> { + w: &'a mut W, +} +impl<'a> ERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub struct MC0_R(crate::FieldReader<bool, bool>); +impl MC0_R { + pub(crate) fn new(bits: bool) -> Self { + MC0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub struct MC0_W<'a> { + w: &'a mut W, +} +impl<'a> MC0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4); + self.w + } +} +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub struct MC1_R(crate::FieldReader<bool, bool>); +impl MC1_R { + pub(crate) fn new(bits: bool) -> Self { + MC1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MC1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub struct MC1_W<'a> { + w: &'a mut W, +} +impl<'a> MC1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u8 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&mut self) -> OVF_W { + OVF_W { w: self } + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&mut self) -> ERR_W { + ERR_W { w: self } + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&mut self) -> MC0_W { + MC0_W { w: self } + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&mut self) -> MC1_W { + MC1_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} |
