diff options
Diffstat (limited to 'src/dmac')
| -rw-r--r-- | src/dmac/active.rs | 166 | ||||
| -rw-r--r-- | src/dmac/baseaddr.rs | 102 | ||||
| -rw-r--r-- | src/dmac/busych.rs | 261 | ||||
| -rw-r--r-- | src/dmac/chctrla.rs | 204 | ||||
| -rw-r--r-- | src/dmac/chctrlb.rs | 1480 | ||||
| -rw-r--r-- | src/dmac/chid.rs | 102 | ||||
| -rw-r--r-- | src/dmac/chintenclr.rs | 204 | ||||
| -rw-r--r-- | src/dmac/chintenset.rs | 204 | ||||
| -rw-r--r-- | src/dmac/chintflag.rs | 204 | ||||
| -rw-r--r-- | src/dmac/chstatus.rs | 90 | ||||
| -rw-r--r-- | src/dmac/crcchksum.rs | 102 | ||||
| -rw-r--r-- | src/dmac/crcctrl.rs | 334 | ||||
| -rw-r--r-- | src/dmac/crcdatain.rs | 102 | ||||
| -rw-r--r-- | src/dmac/crcstatus.rs | 158 | ||||
| -rw-r--r-- | src/dmac/ctrl.rs | 388 | ||||
| -rw-r--r-- | src/dmac/dbgctrl.rs | 112 | ||||
| -rw-r--r-- | src/dmac/intpend.rs | 378 | ||||
| -rw-r--r-- | src/dmac/intstatus.rs | 261 | ||||
| -rw-r--r-- | src/dmac/pendch.rs | 261 | ||||
| -rw-r--r-- | src/dmac/prictrl0.rs | 441 | ||||
| -rw-r--r-- | src/dmac/qosctrl.rs | 399 | ||||
| -rw-r--r-- | src/dmac/swtrigctrl.rs | 618 | ||||
| -rw-r--r-- | src/dmac/wrbaddr.rs | 102 |
23 files changed, 6673 insertions, 0 deletions
diff --git a/src/dmac/active.rs b/src/dmac/active.rs new file mode 100644 index 0000000..d172f45 --- /dev/null +++ b/src/dmac/active.rs @@ -0,0 +1,166 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R<ACTIVE_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<ACTIVE_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<ACTIVE_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<ACTIVE_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub struct LVLEX0_R(crate::FieldReader<bool, bool>); +impl LVLEX0_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEX0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub struct LVLEX1_R(crate::FieldReader<bool, bool>); +impl LVLEX1_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEX1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub struct LVLEX2_R(crate::FieldReader<bool, bool>); +impl LVLEX2_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEX2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub struct LVLEX3_R(crate::FieldReader<bool, bool>); +impl LVLEX3_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEX3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEX3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` reader - Active Channel ID"] +pub struct ID_R(crate::FieldReader<u8, u8>); +impl ID_R { + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub struct ABUSY_R(crate::FieldReader<bool, bool>); +impl ABUSY_R { + pub(crate) fn new(bits: bool) -> Self { + ABUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ABUSY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub struct BTCNT_R(crate::FieldReader<u16, u16>); +impl BTCNT_R { + pub(crate) fn new(bits: u16) -> Self { + BTCNT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BTCNT_R { + type Target = crate::FieldReader<u16, u16>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/baseaddr.rs b/src/dmac/baseaddr.rs new file mode 100644 index 0000000..71ad63e --- /dev/null +++ b/src/dmac/baseaddr.rs @@ -0,0 +1,102 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R<BASEADDR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<BASEADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<BASEADDR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<BASEADDR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W<BASEADDR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<BASEADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<BASEADDR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<BASEADDR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub struct BASEADDR_R(crate::FieldReader<u32, u32>); +impl BASEADDR_R { + pub(crate) fn new(bits: u32) -> Self { + BASEADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BASEADDR_R { + type Target = crate::FieldReader<u32, u32>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub struct BASEADDR_W<'a> { + w: &'a mut W, +} +impl<'a> BASEADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&mut self) -> BASEADDR_W { + BASEADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/busych.rs b/src/dmac/busych.rs new file mode 100644 index 0000000..8ccb81e --- /dev/null +++ b/src/dmac/busych.rs @@ -0,0 +1,261 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R<BUSYCH_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<BUSYCH_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<BUSYCH_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<BUSYCH_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub struct BUSYCH0_R(crate::FieldReader<bool, bool>); +impl BUSYCH0_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub struct BUSYCH1_R(crate::FieldReader<bool, bool>); +impl BUSYCH1_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub struct BUSYCH2_R(crate::FieldReader<bool, bool>); +impl BUSYCH2_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub struct BUSYCH3_R(crate::FieldReader<bool, bool>); +impl BUSYCH3_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub struct BUSYCH4_R(crate::FieldReader<bool, bool>); +impl BUSYCH4_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH4_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub struct BUSYCH5_R(crate::FieldReader<bool, bool>); +impl BUSYCH5_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH5_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub struct BUSYCH6_R(crate::FieldReader<bool, bool>); +impl BUSYCH6_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH6_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub struct BUSYCH7_R(crate::FieldReader<bool, bool>); +impl BUSYCH7_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH7_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub struct BUSYCH8_R(crate::FieldReader<bool, bool>); +impl BUSYCH8_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH8_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub struct BUSYCH9_R(crate::FieldReader<bool, bool>); +impl BUSYCH9_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH9_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub struct BUSYCH10_R(crate::FieldReader<bool, bool>); +impl BUSYCH10_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH10_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub struct BUSYCH11_R(crate::FieldReader<bool, bool>); +impl BUSYCH11_R { + pub(crate) fn new(bits: bool) -> Self { + BUSYCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSYCH11_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chctrla.rs b/src/dmac/chctrla.rs new file mode 100644 index 0000000..d8ce503 --- /dev/null +++ b/src/dmac/chctrla.rs @@ -0,0 +1,204 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R<CHCTRLA_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHCTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHCTRLA_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHCTRLA_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W<CHCTRLA_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHCTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHCTRLA_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHCTRLA_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub struct SWRST_R(crate::FieldReader<bool, bool>); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chctrlb.rs b/src/dmac/chctrlb.rs new file mode 100644 index 0000000..97de2a4 --- /dev/null +++ b/src/dmac/chctrlb.rs @@ -0,0 +1,1480 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R<CHCTRLB_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHCTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHCTRLB_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHCTRLB_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W<CHCTRLB_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHCTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHCTRLB_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHCTRLB_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum EVACT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From<EVACT_A> for u8 { + #[inline(always)] + fn from(variant: EVACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub struct EVACT_R(crate::FieldReader<u8, EVACT_A>); +impl EVACT_R { + pub(crate) fn new(bits: u8) -> Self { + EVACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<EVACT_A> { + match self.bits { + 0 => Some(EVACT_A::NOACT), + 1 => Some(EVACT_A::TRIG), + 2 => Some(EVACT_A::CTRIG), + 3 => Some(EVACT_A::CBLOCK), + 4 => Some(EVACT_A::SUSPEND), + 5 => Some(EVACT_A::RESUME), + 6 => Some(EVACT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == EVACT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + **self == EVACT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + **self == EVACT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + **self == EVACT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == EVACT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == EVACT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + **self == EVACT_A::SSKIP + } +} +impl core::ops::Deref for EVACT_R { + type Target = crate::FieldReader<u8, EVACT_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub struct EVACT_W<'a> { + w: &'a mut W, +} +impl<'a> EVACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: EVACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACT_A::SSKIP) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07); + self.w + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub struct EVIE_R(crate::FieldReader<bool, bool>); +impl EVIE_R { + pub(crate) fn new(bits: bool) -> Self { + EVIE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVIE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub struct EVIE_W<'a> { + w: &'a mut W, +} +impl<'a> EVIE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub struct EVOE_R(crate::FieldReader<bool, bool>); +impl EVOE_R { + pub(crate) fn new(bits: bool) -> Self { + EVOE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVOE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub struct EVOE_W<'a> { + w: &'a mut W, +} +impl<'a> EVOE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Channel Arbitration Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LVL_A { + #[doc = "0: Channel Priority Level 0"] + LVL0 = 0, + #[doc = "1: Channel Priority Level 1"] + LVL1 = 1, + #[doc = "2: Channel Priority Level 2"] + LVL2 = 2, + #[doc = "3: Channel Priority Level 3"] + LVL3 = 3, +} +impl From<LVL_A> for u8 { + #[inline(always)] + fn from(variant: LVL_A) -> Self { + variant as _ + } +} +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub struct LVL_R(crate::FieldReader<u8, LVL_A>); +impl LVL_R { + pub(crate) fn new(bits: u8) -> Self { + LVL_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LVL_A { + match self.bits { + 0 => LVL_A::LVL0, + 1 => LVL_A::LVL1, + 2 => LVL_A::LVL2, + 3 => LVL_A::LVL3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LVL0`"] + #[inline(always)] + pub fn is_lvl0(&self) -> bool { + **self == LVL_A::LVL0 + } + #[doc = "Checks if the value of the field is `LVL1`"] + #[inline(always)] + pub fn is_lvl1(&self) -> bool { + **self == LVL_A::LVL1 + } + #[doc = "Checks if the value of the field is `LVL2`"] + #[inline(always)] + pub fn is_lvl2(&self) -> bool { + **self == LVL_A::LVL2 + } + #[doc = "Checks if the value of the field is `LVL3`"] + #[inline(always)] + pub fn is_lvl3(&self) -> bool { + **self == LVL_A::LVL3 + } +} +impl core::ops::Deref for LVL_R { + type Target = crate::FieldReader<u8, LVL_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub struct LVL_W<'a> { + w: &'a mut W, +} +impl<'a> LVL_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LVL_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Channel Priority Level 0"] + #[inline(always)] + pub fn lvl0(self) -> &'a mut W { + self.variant(LVL_A::LVL0) + } + #[doc = "Channel Priority Level 1"] + #[inline(always)] + pub fn lvl1(self) -> &'a mut W { + self.variant(LVL_A::LVL1) + } + #[doc = "Channel Priority Level 2"] + #[inline(always)] + pub fn lvl2(self) -> &'a mut W { + self.variant(LVL_A::LVL2) + } + #[doc = "Channel Priority Level 3"] + #[inline(always)] + pub fn lvl3(self) -> &'a mut W { + self.variant(LVL_A::LVL3) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5); + self.w + } +} +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGSRC_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, + #[doc = "1: TSENS Result Ready Trigger"] + TSENS = 1, + #[doc = "2: SERCOM0 RX Trigger"] + SERCOM0_RX = 2, + #[doc = "3: SERCOM0 TX Trigger"] + SERCOM0_TX = 3, + #[doc = "4: SERCOM1 RX Trigger"] + SERCOM1_RX = 4, + #[doc = "5: SERCOM1 TX Trigger"] + SERCOM1_TX = 5, + #[doc = "6: SERCOM2 RX Trigger"] + SERCOM2_RX = 6, + #[doc = "7: SERCOM2 TX Trigger"] + SERCOM2_TX = 7, + #[doc = "8: SERCOM3 RX Trigger"] + SERCOM3_RX = 8, + #[doc = "9: SERCOM3 TX Trigger"] + SERCOM3_TX = 9, + #[doc = "10: SERCOM4 RX Trigger"] + SERCOM4_RX = 10, + #[doc = "11: SERCOM4 TX Trigger"] + SERCOM4_TX = 11, + #[doc = "12: SERCOM5 RX Trigger"] + SERCOM5_RX = 12, + #[doc = "13: SERCOM5 TX Trigger"] + SERCOM5_TX = 13, + #[doc = "14: CAN0 Debug Trigger Reserved"] + CAN0_DEBUG = 14, + #[doc = "15: CAN1 Debug Trigger Reserved"] + CAN1_DEBUG = 15, + #[doc = "16: TCC0 Overflow Trigger"] + TCC0_OVF = 16, + #[doc = "17: TCC0 Match/Compare 0 Trigger"] + TCC0_MC0 = 17, + #[doc = "18: TCC0 Match/Compare 1 Trigger"] + TCC0_MC1 = 18, + #[doc = "19: TCC0 Match/Compare 2 Trigger"] + TCC0_MC2 = 19, + #[doc = "20: TCC0 Match/Compare 3 Trigger"] + TCC0_MC3 = 20, + #[doc = "21: TCC1 Overflow Trigger"] + TCC1_OVF = 21, + #[doc = "22: TCC1 Match/Compare 0 Trigger"] + TCC1_MC0 = 22, + #[doc = "23: TCC1 Match/Compare 1 Trigger"] + TCC1_MC1 = 23, + #[doc = "24: TCC2 Overflow Trigger"] + TCC2_OVF = 24, + #[doc = "25: TCC2 Match/Compare 0 Trigger"] + TCC2_MC0 = 25, + #[doc = "26: TCC2 Match/Compare 1 Trigger"] + TCC2_MC1 = 26, + #[doc = "27: TC0 Overflow Trigger"] + TC0_OVF = 27, + #[doc = "28: TC0 Match/Compare 0 Trigger"] + TC0_MC0 = 28, + #[doc = "29: TC0 Match/Compare 1 Trigger"] + TC0_MC1 = 29, + #[doc = "30: TC1 Overflow Trigger"] + TC1_OVF = 30, + #[doc = "31: TC1 Match/Compare 0 Trigger"] + TC1_MC0 = 31, + #[doc = "32: TC1 Match/Compare 1 Trigger"] + TC1_MC1 = 32, + #[doc = "33: TC2 Overflow Trigger"] + TC2_OVF = 33, + #[doc = "34: TC2 Match/Compare 0 Trigger"] + TC2_MC0 = 34, + #[doc = "35: TC2 Match/Compare 1 Trigger"] + TC2_MC1 = 35, + #[doc = "36: TC3 Overflow Trigger"] + TC3_OVF = 36, + #[doc = "37: TC3 Match/Compare 0 Trigger"] + TC3_MC0 = 37, + #[doc = "38: TC3 Match/Compare 1 Trigger"] + TC3_MC1 = 38, + #[doc = "39: TC4 Overflow Trigger"] + TC4_OVF = 39, + #[doc = "40: TC4 Match/Compare 0 Trigger"] + TC4_MC0 = 40, + #[doc = "41: TC4 Match/Compare 1 Trigger"] + TC4_MC1 = 41, + #[doc = "42: ADC0 Result Ready Trigger"] + ADC0_RESRDY = 42, + #[doc = "43: ADC1 Result Ready Trigger"] + ADC1_RESRDY = 43, + #[doc = "44: SDADC Result Ready Trigger"] + SDADC_RESRDY = 44, + #[doc = "45: DAC Empty Trigger"] + DAC_EMPTY = 45, + #[doc = "46: PTC End of Conversion Trigger"] + PTC_EOC = 46, + #[doc = "47: PTC Window Compare Trigger"] + PTC_WCOMP = 47, + #[doc = "48: PTC Sequence Trigger"] + PTC_SEQ = 48, + #[doc = "49: SERCOM6 RX Trigger"] + SERCOM6_RX = 49, + #[doc = "50: SERCOM6 TX Trigger"] + SERCOM6_TX = 50, + #[doc = "51: SERCOM7 RX Trigger"] + SERCOM7_RX = 51, + #[doc = "52: SERCOM7 TX Trigger"] + SERCOM7_TX = 52, + #[doc = "53: TC5 Overflow Trigger"] + TC5_OVF = 53, + #[doc = "54: TC5 Match/Compare 0 Trigger"] + TC5_MC0 = 54, + #[doc = "55: TC5 Match/Compare 1 Trigger"] + TC5_MC1 = 55, + #[doc = "56: TC6 Overflow Trigger"] + TC6_OVF = 56, + #[doc = "57: TC6 Match/Compare 0 Trigger"] + TC6_MC0 = 57, + #[doc = "58: TC6 Match/Compare 1 Trigger"] + TC6_MC1 = 58, + #[doc = "59: TC7 Overflow Trigger"] + TC7_OVF = 59, + #[doc = "60: TC7 Match/Compare 0 Trigger"] + TC7_MC0 = 60, + #[doc = "61: TC7 Match/Compare 1 Trigger"] + TC7_MC1 = 61, +} +impl From<TRIGSRC_A> for u8 { + #[inline(always)] + fn from(variant: TRIGSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub struct TRIGSRC_R(crate::FieldReader<u8, TRIGSRC_A>); +impl TRIGSRC_R { + pub(crate) fn new(bits: u8) -> Self { + TRIGSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<TRIGSRC_A> { + match self.bits { + 0 => Some(TRIGSRC_A::DISABLE), + 1 => Some(TRIGSRC_A::TSENS), + 2 => Some(TRIGSRC_A::SERCOM0_RX), + 3 => Some(TRIGSRC_A::SERCOM0_TX), + 4 => Some(TRIGSRC_A::SERCOM1_RX), + 5 => Some(TRIGSRC_A::SERCOM1_TX), + 6 => Some(TRIGSRC_A::SERCOM2_RX), + 7 => Some(TRIGSRC_A::SERCOM2_TX), + 8 => Some(TRIGSRC_A::SERCOM3_RX), + 9 => Some(TRIGSRC_A::SERCOM3_TX), + 10 => Some(TRIGSRC_A::SERCOM4_RX), + 11 => Some(TRIGSRC_A::SERCOM4_TX), + 12 => Some(TRIGSRC_A::SERCOM5_RX), + 13 => Some(TRIGSRC_A::SERCOM5_TX), + 14 => Some(TRIGSRC_A::CAN0_DEBUG), + 15 => Some(TRIGSRC_A::CAN1_DEBUG), + 16 => Some(TRIGSRC_A::TCC0_OVF), + 17 => Some(TRIGSRC_A::TCC0_MC0), + 18 => Some(TRIGSRC_A::TCC0_MC1), + 19 => Some(TRIGSRC_A::TCC0_MC2), + 20 => Some(TRIGSRC_A::TCC0_MC3), + 21 => Some(TRIGSRC_A::TCC1_OVF), + 22 => Some(TRIGSRC_A::TCC1_MC0), + 23 => Some(TRIGSRC_A::TCC1_MC1), + 24 => Some(TRIGSRC_A::TCC2_OVF), + 25 => Some(TRIGSRC_A::TCC2_MC0), + 26 => Some(TRIGSRC_A::TCC2_MC1), + 27 => Some(TRIGSRC_A::TC0_OVF), + 28 => Some(TRIGSRC_A::TC0_MC0), + 29 => Some(TRIGSRC_A::TC0_MC1), + 30 => Some(TRIGSRC_A::TC1_OVF), + 31 => Some(TRIGSRC_A::TC1_MC0), + 32 => Some(TRIGSRC_A::TC1_MC1), + 33 => Some(TRIGSRC_A::TC2_OVF), + 34 => Some(TRIGSRC_A::TC2_MC0), + 35 => Some(TRIGSRC_A::TC2_MC1), + 36 => Some(TRIGSRC_A::TC3_OVF), + 37 => Some(TRIGSRC_A::TC3_MC0), + 38 => Some(TRIGSRC_A::TC3_MC1), + 39 => Some(TRIGSRC_A::TC4_OVF), + 40 => Some(TRIGSRC_A::TC4_MC0), + 41 => Some(TRIGSRC_A::TC4_MC1), + 42 => Some(TRIGSRC_A::ADC0_RESRDY), + 43 => Some(TRIGSRC_A::ADC1_RESRDY), + 44 => Some(TRIGSRC_A::SDADC_RESRDY), + 45 => Some(TRIGSRC_A::DAC_EMPTY), + 46 => Some(TRIGSRC_A::PTC_EOC), + 47 => Some(TRIGSRC_A::PTC_WCOMP), + 48 => Some(TRIGSRC_A::PTC_SEQ), + 49 => Some(TRIGSRC_A::SERCOM6_RX), + 50 => Some(TRIGSRC_A::SERCOM6_TX), + 51 => Some(TRIGSRC_A::SERCOM7_RX), + 52 => Some(TRIGSRC_A::SERCOM7_TX), + 53 => Some(TRIGSRC_A::TC5_OVF), + 54 => Some(TRIGSRC_A::TC5_MC0), + 55 => Some(TRIGSRC_A::TC5_MC1), + 56 => Some(TRIGSRC_A::TC6_OVF), + 57 => Some(TRIGSRC_A::TC6_MC0), + 58 => Some(TRIGSRC_A::TC6_MC1), + 59 => Some(TRIGSRC_A::TC7_OVF), + 60 => Some(TRIGSRC_A::TC7_MC0), + 61 => Some(TRIGSRC_A::TC7_MC1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == TRIGSRC_A::DISABLE + } + #[doc = "Checks if the value of the field is `TSENS`"] + #[inline(always)] + pub fn is_tsens(&self) -> bool { + **self == TRIGSRC_A::TSENS + } + #[doc = "Checks if the value of the field is `SERCOM0_RX`"] + #[inline(always)] + pub fn is_sercom0_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_RX + } + #[doc = "Checks if the value of the field is `SERCOM0_TX`"] + #[inline(always)] + pub fn is_sercom0_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM0_TX + } + #[doc = "Checks if the value of the field is `SERCOM1_RX`"] + #[inline(always)] + pub fn is_sercom1_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_RX + } + #[doc = "Checks if the value of the field is `SERCOM1_TX`"] + #[inline(always)] + pub fn is_sercom1_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM1_TX + } + #[doc = "Checks if the value of the field is `SERCOM2_RX`"] + #[inline(always)] + pub fn is_sercom2_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_RX + } + #[doc = "Checks if the value of the field is `SERCOM2_TX`"] + #[inline(always)] + pub fn is_sercom2_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM2_TX + } + #[doc = "Checks if the value of the field is `SERCOM3_RX`"] + #[inline(always)] + pub fn is_sercom3_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_RX + } + #[doc = "Checks if the value of the field is `SERCOM3_TX`"] + #[inline(always)] + pub fn is_sercom3_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM3_TX + } + #[doc = "Checks if the value of the field is `SERCOM4_RX`"] + #[inline(always)] + pub fn is_sercom4_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_RX + } + #[doc = "Checks if the value of the field is `SERCOM4_TX`"] + #[inline(always)] + pub fn is_sercom4_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM4_TX + } + #[doc = "Checks if the value of the field is `SERCOM5_RX`"] + #[inline(always)] + pub fn is_sercom5_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_RX + } + #[doc = "Checks if the value of the field is `SERCOM5_TX`"] + #[inline(always)] + pub fn is_sercom5_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM5_TX + } + #[doc = "Checks if the value of the field is `CAN0_DEBUG`"] + #[inline(always)] + pub fn is_can0_debug(&self) -> bool { + **self == TRIGSRC_A::CAN0_DEBUG + } + #[doc = "Checks if the value of the field is `CAN1_DEBUG`"] + #[inline(always)] + pub fn is_can1_debug(&self) -> bool { + **self == TRIGSRC_A::CAN1_DEBUG + } + #[doc = "Checks if the value of the field is `TCC0_OVF`"] + #[inline(always)] + pub fn is_tcc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC0_OVF + } + #[doc = "Checks if the value of the field is `TCC0_MC0`"] + #[inline(always)] + pub fn is_tcc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC0 + } + #[doc = "Checks if the value of the field is `TCC0_MC1`"] + #[inline(always)] + pub fn is_tcc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC1 + } + #[doc = "Checks if the value of the field is `TCC0_MC2`"] + #[inline(always)] + pub fn is_tcc0_mc2(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC2 + } + #[doc = "Checks if the value of the field is `TCC0_MC3`"] + #[inline(always)] + pub fn is_tcc0_mc3(&self) -> bool { + **self == TRIGSRC_A::TCC0_MC3 + } + #[doc = "Checks if the value of the field is `TCC1_OVF`"] + #[inline(always)] + pub fn is_tcc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC1_OVF + } + #[doc = "Checks if the value of the field is `TCC1_MC0`"] + #[inline(always)] + pub fn is_tcc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC0 + } + #[doc = "Checks if the value of the field is `TCC1_MC1`"] + #[inline(always)] + pub fn is_tcc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC1_MC1 + } + #[doc = "Checks if the value of the field is `TCC2_OVF`"] + #[inline(always)] + pub fn is_tcc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TCC2_OVF + } + #[doc = "Checks if the value of the field is `TCC2_MC0`"] + #[inline(always)] + pub fn is_tcc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC0 + } + #[doc = "Checks if the value of the field is `TCC2_MC1`"] + #[inline(always)] + pub fn is_tcc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TCC2_MC1 + } + #[doc = "Checks if the value of the field is `TC0_OVF`"] + #[inline(always)] + pub fn is_tc0_ovf(&self) -> bool { + **self == TRIGSRC_A::TC0_OVF + } + #[doc = "Checks if the value of the field is `TC0_MC0`"] + #[inline(always)] + pub fn is_tc0_mc0(&self) -> bool { + **self == TRIGSRC_A::TC0_MC0 + } + #[doc = "Checks if the value of the field is `TC0_MC1`"] + #[inline(always)] + pub fn is_tc0_mc1(&self) -> bool { + **self == TRIGSRC_A::TC0_MC1 + } + #[doc = "Checks if the value of the field is `TC1_OVF`"] + #[inline(always)] + pub fn is_tc1_ovf(&self) -> bool { + **self == TRIGSRC_A::TC1_OVF + } + #[doc = "Checks if the value of the field is `TC1_MC0`"] + #[inline(always)] + pub fn is_tc1_mc0(&self) -> bool { + **self == TRIGSRC_A::TC1_MC0 + } + #[doc = "Checks if the value of the field is `TC1_MC1`"] + #[inline(always)] + pub fn is_tc1_mc1(&self) -> bool { + **self == TRIGSRC_A::TC1_MC1 + } + #[doc = "Checks if the value of the field is `TC2_OVF`"] + #[inline(always)] + pub fn is_tc2_ovf(&self) -> bool { + **self == TRIGSRC_A::TC2_OVF + } + #[doc = "Checks if the value of the field is `TC2_MC0`"] + #[inline(always)] + pub fn is_tc2_mc0(&self) -> bool { + **self == TRIGSRC_A::TC2_MC0 + } + #[doc = "Checks if the value of the field is `TC2_MC1`"] + #[inline(always)] + pub fn is_tc2_mc1(&self) -> bool { + **self == TRIGSRC_A::TC2_MC1 + } + #[doc = "Checks if the value of the field is `TC3_OVF`"] + #[inline(always)] + pub fn is_tc3_ovf(&self) -> bool { + **self == TRIGSRC_A::TC3_OVF + } + #[doc = "Checks if the value of the field is `TC3_MC0`"] + #[inline(always)] + pub fn is_tc3_mc0(&self) -> bool { + **self == TRIGSRC_A::TC3_MC0 + } + #[doc = "Checks if the value of the field is `TC3_MC1`"] + #[inline(always)] + pub fn is_tc3_mc1(&self) -> bool { + **self == TRIGSRC_A::TC3_MC1 + } + #[doc = "Checks if the value of the field is `TC4_OVF`"] + #[inline(always)] + pub fn is_tc4_ovf(&self) -> bool { + **self == TRIGSRC_A::TC4_OVF + } + #[doc = "Checks if the value of the field is `TC4_MC0`"] + #[inline(always)] + pub fn is_tc4_mc0(&self) -> bool { + **self == TRIGSRC_A::TC4_MC0 + } + #[doc = "Checks if the value of the field is `TC4_MC1`"] + #[inline(always)] + pub fn is_tc4_mc1(&self) -> bool { + **self == TRIGSRC_A::TC4_MC1 + } + #[doc = "Checks if the value of the field is `ADC0_RESRDY`"] + #[inline(always)] + pub fn is_adc0_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC0_RESRDY + } + #[doc = "Checks if the value of the field is `ADC1_RESRDY`"] + #[inline(always)] + pub fn is_adc1_resrdy(&self) -> bool { + **self == TRIGSRC_A::ADC1_RESRDY + } + #[doc = "Checks if the value of the field is `SDADC_RESRDY`"] + #[inline(always)] + pub fn is_sdadc_resrdy(&self) -> bool { + **self == TRIGSRC_A::SDADC_RESRDY + } + #[doc = "Checks if the value of the field is `DAC_EMPTY`"] + #[inline(always)] + pub fn is_dac_empty(&self) -> bool { + **self == TRIGSRC_A::DAC_EMPTY + } + #[doc = "Checks if the value of the field is `PTC_EOC`"] + #[inline(always)] + pub fn is_ptc_eoc(&self) -> bool { + **self == TRIGSRC_A::PTC_EOC + } + #[doc = "Checks if the value of the field is `PTC_WCOMP`"] + #[inline(always)] + pub fn is_ptc_wcomp(&self) -> bool { + **self == TRIGSRC_A::PTC_WCOMP + } + #[doc = "Checks if the value of the field is `PTC_SEQ`"] + #[inline(always)] + pub fn is_ptc_seq(&self) -> bool { + **self == TRIGSRC_A::PTC_SEQ + } + #[doc = "Checks if the value of the field is `SERCOM6_RX`"] + #[inline(always)] + pub fn is_sercom6_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_RX + } + #[doc = "Checks if the value of the field is `SERCOM6_TX`"] + #[inline(always)] + pub fn is_sercom6_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM6_TX + } + #[doc = "Checks if the value of the field is `SERCOM7_RX`"] + #[inline(always)] + pub fn is_sercom7_rx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_RX + } + #[doc = "Checks if the value of the field is `SERCOM7_TX`"] + #[inline(always)] + pub fn is_sercom7_tx(&self) -> bool { + **self == TRIGSRC_A::SERCOM7_TX + } + #[doc = "Checks if the value of the field is `TC5_OVF`"] + #[inline(always)] + pub fn is_tc5_ovf(&self) -> bool { + **self == TRIGSRC_A::TC5_OVF + } + #[doc = "Checks if the value of the field is `TC5_MC0`"] + #[inline(always)] + pub fn is_tc5_mc0(&self) -> bool { + **self == TRIGSRC_A::TC5_MC0 + } + #[doc = "Checks if the value of the field is `TC5_MC1`"] + #[inline(always)] + pub fn is_tc5_mc1(&self) -> bool { + **self == TRIGSRC_A::TC5_MC1 + } + #[doc = "Checks if the value of the field is `TC6_OVF`"] + #[inline(always)] + pub fn is_tc6_ovf(&self) -> bool { + **self == TRIGSRC_A::TC6_OVF + } + #[doc = "Checks if the value of the field is `TC6_MC0`"] + #[inline(always)] + pub fn is_tc6_mc0(&self) -> bool { + **self == TRIGSRC_A::TC6_MC0 + } + #[doc = "Checks if the value of the field is `TC6_MC1`"] + #[inline(always)] + pub fn is_tc6_mc1(&self) -> bool { + **self == TRIGSRC_A::TC6_MC1 + } + #[doc = "Checks if the value of the field is `TC7_OVF`"] + #[inline(always)] + pub fn is_tc7_ovf(&self) -> bool { + **self == TRIGSRC_A::TC7_OVF + } + #[doc = "Checks if the value of the field is `TC7_MC0`"] + #[inline(always)] + pub fn is_tc7_mc0(&self) -> bool { + **self == TRIGSRC_A::TC7_MC0 + } + #[doc = "Checks if the value of the field is `TC7_MC1`"] + #[inline(always)] + pub fn is_tc7_mc1(&self) -> bool { + **self == TRIGSRC_A::TC7_MC1 + } +} +impl core::ops::Deref for TRIGSRC_R { + type Target = crate::FieldReader<u8, TRIGSRC_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub struct TRIGSRC_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRC_A::DISABLE) + } + #[doc = "TSENS Result Ready Trigger"] + #[inline(always)] + pub fn tsens(self) -> &'a mut W { + self.variant(TRIGSRC_A::TSENS) + } + #[doc = "SERCOM0 RX Trigger"] + #[inline(always)] + pub fn sercom0_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_RX) + } + #[doc = "SERCOM0 TX Trigger"] + #[inline(always)] + pub fn sercom0_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM0_TX) + } + #[doc = "SERCOM1 RX Trigger"] + #[inline(always)] + pub fn sercom1_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_RX) + } + #[doc = "SERCOM1 TX Trigger"] + #[inline(always)] + pub fn sercom1_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM1_TX) + } + #[doc = "SERCOM2 RX Trigger"] + #[inline(always)] + pub fn sercom2_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_RX) + } + #[doc = "SERCOM2 TX Trigger"] + #[inline(always)] + pub fn sercom2_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM2_TX) + } + #[doc = "SERCOM3 RX Trigger"] + #[inline(always)] + pub fn sercom3_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_RX) + } + #[doc = "SERCOM3 TX Trigger"] + #[inline(always)] + pub fn sercom3_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM3_TX) + } + #[doc = "SERCOM4 RX Trigger"] + #[inline(always)] + pub fn sercom4_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_RX) + } + #[doc = "SERCOM4 TX Trigger"] + #[inline(always)] + pub fn sercom4_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM4_TX) + } + #[doc = "SERCOM5 RX Trigger"] + #[inline(always)] + pub fn sercom5_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_RX) + } + #[doc = "SERCOM5 TX Trigger"] + #[inline(always)] + pub fn sercom5_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM5_TX) + } + #[doc = "CAN0 Debug Trigger Reserved"] + #[inline(always)] + pub fn can0_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN0_DEBUG) + } + #[doc = "CAN1 Debug Trigger Reserved"] + #[inline(always)] + pub fn can1_debug(self) -> &'a mut W { + self.variant(TRIGSRC_A::CAN1_DEBUG) + } + #[doc = "TCC0 Overflow Trigger"] + #[inline(always)] + pub fn tcc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_OVF) + } + #[doc = "TCC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC0) + } + #[doc = "TCC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC1) + } + #[doc = "TCC0 Match/Compare 2 Trigger"] + #[inline(always)] + pub fn tcc0_mc2(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC2) + } + #[doc = "TCC0 Match/Compare 3 Trigger"] + #[inline(always)] + pub fn tcc0_mc3(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC0_MC3) + } + #[doc = "TCC1 Overflow Trigger"] + #[inline(always)] + pub fn tcc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_OVF) + } + #[doc = "TCC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC0) + } + #[doc = "TCC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC1_MC1) + } + #[doc = "TCC2 Overflow Trigger"] + #[inline(always)] + pub fn tcc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_OVF) + } + #[doc = "TCC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tcc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC0) + } + #[doc = "TCC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tcc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TCC2_MC1) + } + #[doc = "TC0 Overflow Trigger"] + #[inline(always)] + pub fn tc0_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_OVF) + } + #[doc = "TC0 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc0_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC0) + } + #[doc = "TC0 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc0_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC0_MC1) + } + #[doc = "TC1 Overflow Trigger"] + #[inline(always)] + pub fn tc1_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_OVF) + } + #[doc = "TC1 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc1_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC0) + } + #[doc = "TC1 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc1_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC1_MC1) + } + #[doc = "TC2 Overflow Trigger"] + #[inline(always)] + pub fn tc2_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_OVF) + } + #[doc = "TC2 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc2_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC0) + } + #[doc = "TC2 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc2_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC2_MC1) + } + #[doc = "TC3 Overflow Trigger"] + #[inline(always)] + pub fn tc3_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_OVF) + } + #[doc = "TC3 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc3_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC0) + } + #[doc = "TC3 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc3_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC3_MC1) + } + #[doc = "TC4 Overflow Trigger"] + #[inline(always)] + pub fn tc4_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_OVF) + } + #[doc = "TC4 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc4_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC0) + } + #[doc = "TC4 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc4_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC4_MC1) + } + #[doc = "ADC0 Result Ready Trigger"] + #[inline(always)] + pub fn adc0_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC0_RESRDY) + } + #[doc = "ADC1 Result Ready Trigger"] + #[inline(always)] + pub fn adc1_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::ADC1_RESRDY) + } + #[doc = "SDADC Result Ready Trigger"] + #[inline(always)] + pub fn sdadc_resrdy(self) -> &'a mut W { + self.variant(TRIGSRC_A::SDADC_RESRDY) + } + #[doc = "DAC Empty Trigger"] + #[inline(always)] + pub fn dac_empty(self) -> &'a mut W { + self.variant(TRIGSRC_A::DAC_EMPTY) + } + #[doc = "PTC End of Conversion Trigger"] + #[inline(always)] + pub fn ptc_eoc(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_EOC) + } + #[doc = "PTC Window Compare Trigger"] + #[inline(always)] + pub fn ptc_wcomp(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_WCOMP) + } + #[doc = "PTC Sequence Trigger"] + #[inline(always)] + pub fn ptc_seq(self) -> &'a mut W { + self.variant(TRIGSRC_A::PTC_SEQ) + } + #[doc = "SERCOM6 RX Trigger"] + #[inline(always)] + pub fn sercom6_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_RX) + } + #[doc = "SERCOM6 TX Trigger"] + #[inline(always)] + pub fn sercom6_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM6_TX) + } + #[doc = "SERCOM7 RX Trigger"] + #[inline(always)] + pub fn sercom7_rx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_RX) + } + #[doc = "SERCOM7 TX Trigger"] + #[inline(always)] + pub fn sercom7_tx(self) -> &'a mut W { + self.variant(TRIGSRC_A::SERCOM7_TX) + } + #[doc = "TC5 Overflow Trigger"] + #[inline(always)] + pub fn tc5_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_OVF) + } + #[doc = "TC5 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc5_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC0) + } + #[doc = "TC5 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc5_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC5_MC1) + } + #[doc = "TC6 Overflow Trigger"] + #[inline(always)] + pub fn tc6_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_OVF) + } + #[doc = "TC6 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc6_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC0) + } + #[doc = "TC6 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc6_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC6_MC1) + } + #[doc = "TC7 Overflow Trigger"] + #[inline(always)] + pub fn tc7_ovf(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_OVF) + } + #[doc = "TC7 Match/Compare 0 Trigger"] + #[inline(always)] + pub fn tc7_mc0(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC0) + } + #[doc = "TC7 Match/Compare 1 Trigger"] + #[inline(always)] + pub fn tc7_mc1(self) -> &'a mut W { + self.variant(TRIGSRC_A::TC7_MC1) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u32 & 0x3f) << 8); + self.w + } +} +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum TRIGACT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From<TRIGACT_A> for u8 { + #[inline(always)] + fn from(variant: TRIGACT_A) -> Self { + variant as _ + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub struct TRIGACT_R(crate::FieldReader<u8, TRIGACT_A>); +impl TRIGACT_R { + pub(crate) fn new(bits: u8) -> Self { + TRIGACT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<TRIGACT_A> { + match self.bits { + 0 => Some(TRIGACT_A::BLOCK), + 2 => Some(TRIGACT_A::BEAT), + 3 => Some(TRIGACT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + **self == TRIGACT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + **self == TRIGACT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + **self == TRIGACT_A::TRANSACTION + } +} +impl core::ops::Deref for TRIGACT_R { + type Target = crate::FieldReader<u8, TRIGACT_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub struct TRIGACT_W<'a> { + w: &'a mut W, +} +impl<'a> TRIGACT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: TRIGACT_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACT_A::TRANSACTION) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 22)) | ((value as u32 & 0x03) << 22); + self.w + } +} +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CMD_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From<CMD_A> for u8 { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as _ + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub struct CMD_R(crate::FieldReader<u8, CMD_A>); +impl CMD_R { + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<CMD_A> { + match self.bits { + 0 => Some(CMD_A::NOACT), + 1 => Some(CMD_A::SUSPEND), + 2 => Some(CMD_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CMD_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + **self == CMD_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + **self == CMD_A::RESUME + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader<u8, CMD_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CMD_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMD_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMD_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMD_A::RESUME) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 0x07) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 0x03) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 0x03) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&mut self) -> EVACT_W { + EVACT_W { w: self } + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&mut self) -> EVIE_W { + EVIE_W { w: self } + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&mut self) -> EVOE_W { + EVOE_W { w: self } + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&mut self) -> LVL_W { + LVL_W { w: self } + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&mut self) -> TRIGSRC_W { + TRIGSRC_W { w: self } + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&mut self) -> TRIGACT_W { + TRIGACT_W { w: self } + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chid.rs b/src/dmac/chid.rs new file mode 100644 index 0000000..4a15300 --- /dev/null +++ b/src/dmac/chid.rs @@ -0,0 +1,102 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R<CHID_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHID_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHID_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHID_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W<CHID_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHID_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHID_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHID_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader<u8, u8>); +impl ID_R { + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chintenclr.rs b/src/dmac/chintenclr.rs new file mode 100644 index 0000000..53d07e8 --- /dev/null +++ b/src/dmac/chintenclr.rs @@ -0,0 +1,204 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R<CHINTENCLR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHINTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHINTENCLR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHINTENCLR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W<CHINTENCLR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHINTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHINTENCLR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHINTENCLR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader<bool, bool>); +impl TERR_R { + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader<bool, bool>); +impl TCMPL_R { + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader<bool, bool>); +impl SUSP_R { + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chintenset.rs b/src/dmac/chintenset.rs new file mode 100644 index 0000000..93efb28 --- /dev/null +++ b/src/dmac/chintenset.rs @@ -0,0 +1,204 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R<CHINTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHINTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHINTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHINTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W<CHINTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHINTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHINTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHINTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub struct TERR_R(crate::FieldReader<bool, bool>); +impl TERR_R { + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_R(crate::FieldReader<bool, bool>); +impl TCMPL_R { + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub struct SUSP_R(crate::FieldReader<bool, bool>); +impl SUSP_R { + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chintflag.rs b/src/dmac/chintflag.rs new file mode 100644 index 0000000..4d1f88f --- /dev/null +++ b/src/dmac/chintflag.rs @@ -0,0 +1,204 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R<CHINTFLAG_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHINTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHINTFLAG_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHINTFLAG_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W<CHINTFLAG_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CHINTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CHINTFLAG_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CHINTFLAG_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub struct TERR_R(crate::FieldReader<bool, bool>); +impl TERR_R { + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader<bool, bool>); +impl TCMPL_R { + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader<bool, bool>); +impl SUSP_R { + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/chstatus.rs b/src/dmac/chstatus.rs new file mode 100644 index 0000000..308a62a --- /dev/null +++ b/src/dmac/chstatus.rs @@ -0,0 +1,90 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R<CHSTATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CHSTATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CHSTATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CHSTATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub struct PEND_R(crate::FieldReader<bool, bool>); +impl PEND_R { + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` reader - Channel Busy"] +pub struct BUSY_R(crate::FieldReader<bool, bool>); +impl BUSY_R { + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub struct FERR_R(crate::FieldReader<bool, bool>); +impl FERR_R { + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/crcchksum.rs b/src/dmac/crcchksum.rs new file mode 100644 index 0000000..335dde1 --- /dev/null +++ b/src/dmac/crcchksum.rs @@ -0,0 +1,102 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R<CRCCHKSUM_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CRCCHKSUM_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CRCCHKSUM_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CRCCHKSUM_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W<CRCCHKSUM_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CRCCHKSUM_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CRCCHKSUM_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CRCCHKSUM_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub struct CRCCHKSUM_R(crate::FieldReader<u32, u32>); +impl CRCCHKSUM_R { + pub(crate) fn new(bits: u32) -> Self { + CRCCHKSUM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCCHKSUM_R { + type Target = crate::FieldReader<u32, u32>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub struct CRCCHKSUM_W<'a> { + w: &'a mut W, +} +impl<'a> CRCCHKSUM_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W { + CRCCHKSUM_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/crcctrl.rs b/src/dmac/crcctrl.rs new file mode 100644 index 0000000..45464cd --- /dev/null +++ b/src/dmac/crcctrl.rs @@ -0,0 +1,334 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R<CRCCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CRCCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CRCCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CRCCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W<CRCCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CRCCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CRCCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CRCCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCBEATSIZE_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From<CRCBEATSIZE_A> for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZE_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub struct CRCBEATSIZE_R(crate::FieldReader<u8, CRCBEATSIZE_A>); +impl CRCBEATSIZE_R { + pub(crate) fn new(bits: u8) -> Self { + CRCBEATSIZE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<CRCBEATSIZE_A> { + match self.bits { + 0 => Some(CRCBEATSIZE_A::BYTE), + 1 => Some(CRCBEATSIZE_A::HWORD), + 2 => Some(CRCBEATSIZE_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + **self == CRCBEATSIZE_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + **self == CRCBEATSIZE_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + **self == CRCBEATSIZE_A::WORD + } +} +impl core::ops::Deref for CRCBEATSIZE_R { + type Target = crate::FieldReader<u8, CRCBEATSIZE_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub struct CRCBEATSIZE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBEATSIZE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCBEATSIZE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZE_A::WORD) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u16 & 0x03); + self.w + } +} +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCPOLY_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From<CRCPOLY_A> for u8 { + #[inline(always)] + fn from(variant: CRCPOLY_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub struct CRCPOLY_R(crate::FieldReader<u8, CRCPOLY_A>); +impl CRCPOLY_R { + pub(crate) fn new(bits: u8) -> Self { + CRCPOLY_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<CRCPOLY_A> { + match self.bits { + 0 => Some(CRCPOLY_A::CRC16), + 1 => Some(CRCPOLY_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + **self == CRCPOLY_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + **self == CRCPOLY_A::CRC32 + } +} +impl core::ops::Deref for CRCPOLY_R { + type Target = crate::FieldReader<u8, CRCPOLY_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub struct CRCPOLY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCPOLY_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCPOLY_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLY_A::CRC32) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u16 & 0x03) << 2); + self.w + } +} +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CRCSRC_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From<CRCSRC_A> for u8 { + #[inline(always)] + fn from(variant: CRCSRC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub struct CRCSRC_R(crate::FieldReader<u8, CRCSRC_A>); +impl CRCSRC_R { + pub(crate) fn new(bits: u8) -> Self { + CRCSRC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<CRCSRC_A> { + match self.bits { + 0 => Some(CRCSRC_A::NOACT), + 1 => Some(CRCSRC_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + **self == CRCSRC_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + **self == CRCSRC_A::IO + } +} +impl core::ops::Deref for CRCSRC_R { + type Target = crate::FieldReader<u8, CRCSRC_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub struct CRCSRC_W<'a> { + w: &'a mut W, +} +impl<'a> CRCSRC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CRCSRC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRC_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRC_A::IO) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 8)) | ((value as u16 & 0x3f) << 8); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W { + CRCBEATSIZE_W { w: self } + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&mut self) -> CRCPOLY_W { + CRCPOLY_W { w: self } + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&mut self) -> CRCSRC_W { + CRCSRC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/crcdatain.rs b/src/dmac/crcdatain.rs new file mode 100644 index 0000000..a421a0c --- /dev/null +++ b/src/dmac/crcdatain.rs @@ -0,0 +1,102 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R<CRCDATAIN_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CRCDATAIN_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CRCDATAIN_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CRCDATAIN_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W<CRCDATAIN_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CRCDATAIN_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CRCDATAIN_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CRCDATAIN_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub struct CRCDATAIN_R(crate::FieldReader<u32, u32>); +impl CRCDATAIN_R { + pub(crate) fn new(bits: u32) -> Self { + CRCDATAIN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCDATAIN_R { + type Target = crate::FieldReader<u32, u32>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub struct CRCDATAIN_W<'a> { + w: &'a mut W, +} +impl<'a> CRCDATAIN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&mut self) -> CRCDATAIN_W { + CRCDATAIN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/crcstatus.rs b/src/dmac/crcstatus.rs new file mode 100644 index 0000000..6595d53 --- /dev/null +++ b/src/dmac/crcstatus.rs @@ -0,0 +1,158 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R<CRCSTATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CRCSTATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CRCSTATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CRCSTATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W<CRCSTATUS_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CRCSTATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CRCSTATUS_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CRCSTATUS_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub struct CRCBUSY_R(crate::FieldReader<bool, bool>); +impl CRCBUSY_R { + pub(crate) fn new(bits: bool) -> Self { + CRCBUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCBUSY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub struct CRCBUSY_W<'a> { + w: &'a mut W, +} +impl<'a> CRCBUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub struct CRCZERO_R(crate::FieldReader<bool, bool>); +impl CRCZERO_R { + pub(crate) fn new(bits: bool) -> Self { + CRCZERO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCZERO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCZERO` writer - CRC Zero"] +pub struct CRCZERO_W<'a> { + w: &'a mut W, +} +impl<'a> CRCZERO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&mut self) -> CRCBUSY_W { + CRCBUSY_W { w: self } + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&mut self) -> CRCZERO_W { + CRCZERO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/ctrl.rs b/src/dmac/ctrl.rs new file mode 100644 index 0000000..bc7d2cc --- /dev/null +++ b/src/dmac/ctrl.rs @@ -0,0 +1,388 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R<CTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W<CTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader<bool, bool>); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub struct DMAENABLE_R(crate::FieldReader<bool, bool>); +impl DMAENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + DMAENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub struct DMAENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> DMAENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub struct CRCENABLE_R(crate::FieldReader<bool, bool>); +impl CRCENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + CRCENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CRCENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub struct CRCENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> CRCENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub struct LVLEN0_R(crate::FieldReader<bool, bool>); +impl LVLEN0_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEN0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub struct LVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub struct LVLEN1_R(crate::FieldReader<bool, bool>); +impl LVLEN1_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub struct LVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub struct LVLEN2_R(crate::FieldReader<bool, bool>); +impl LVLEN2_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub struct LVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub struct LVLEN3_R(crate::FieldReader<bool, bool>); +impl LVLEN3_R { + pub(crate) fn new(bits: bool) -> Self { + LVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLEN3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub struct LVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&mut self) -> DMAENABLE_W { + DMAENABLE_W { w: self } + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&mut self) -> CRCENABLE_W { + CRCENABLE_W { w: self } + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&mut self) -> LVLEN0_W { + LVLEN0_W { w: self } + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&mut self) -> LVLEN1_W { + LVLEN1_W { w: self } + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&mut self) -> LVLEN2_W { + LVLEN2_W { w: self } + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&mut self) -> LVLEN3_W { + LVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/dbgctrl.rs b/src/dmac/dbgctrl.rs new file mode 100644 index 0000000..8befebc --- /dev/null +++ b/src/dmac/dbgctrl.rs @@ -0,0 +1,112 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R<DBGCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DBGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DBGCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DBGCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W<DBGCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DBGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DBGCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DBGCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub struct DBGRUN_R(crate::FieldReader<bool, bool>); +impl DBGRUN_R { + pub(crate) fn new(bits: bool) -> Self { + DBGRUN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGRUN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub struct DBGRUN_W<'a> { + w: &'a mut W, +} +impl<'a> DBGRUN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&mut self) -> DBGRUN_W { + DBGRUN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/intpend.rs b/src/dmac/intpend.rs new file mode 100644 index 0000000..c3d6382 --- /dev/null +++ b/src/dmac/intpend.rs @@ -0,0 +1,378 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R<INTPEND_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTPEND_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTPEND_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTPEND_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W<INTPEND_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTPEND_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTPEND_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTPEND_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub struct ID_R(crate::FieldReader<u8, u8>); +impl ID_R { + pub(crate) fn new(bits: u8) -> Self { + ID_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ID_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ID` writer - Channel ID"] +pub struct ID_W<'a> { + w: &'a mut W, +} +impl<'a> ID_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u16 & 0x0f); + self.w + } +} +#[doc = "Field `TERR` reader - Transfer Error"] +pub struct TERR_R(crate::FieldReader<bool, bool>); +impl TERR_R { + pub(crate) fn new(bits: bool) -> Self { + TERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TERR` writer - Transfer Error"] +pub struct TERR_W<'a> { + w: &'a mut W, +} +impl<'a> TERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub struct TCMPL_R(crate::FieldReader<bool, bool>); +impl TCMPL_R { + pub(crate) fn new(bits: bool) -> Self { + TCMPL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCMPL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub struct TCMPL_W<'a> { + w: &'a mut W, +} +impl<'a> TCMPL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub struct SUSP_R(crate::FieldReader<bool, bool>); +impl SUSP_R { + pub(crate) fn new(bits: bool) -> Self { + SUSP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUSP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub struct SUSP_W<'a> { + w: &'a mut W, +} +impl<'a> SUSP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FERR` reader - Fetch Error"] +pub struct FERR_R(crate::FieldReader<bool, bool>); +impl FERR_R { + pub(crate) fn new(bits: bool) -> Self { + FERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FERR` writer - Fetch Error"] +pub struct FERR_W<'a> { + w: &'a mut W, +} +impl<'a> FERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u16 & 0x01) << 13); + self.w + } +} +#[doc = "Field `BUSY` reader - Busy"] +pub struct BUSY_R(crate::FieldReader<bool, bool>); +impl BUSY_R { + pub(crate) fn new(bits: bool) -> Self { + BUSY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSY` writer - Busy"] +pub struct BUSY_W<'a> { + w: &'a mut W, +} +impl<'a> BUSY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u16 & 0x01) << 14); + self.w + } +} +#[doc = "Field `PEND` reader - Pending"] +pub struct PEND_R(crate::FieldReader<bool, bool>); +impl PEND_R { + pub(crate) fn new(bits: bool) -> Self { + PEND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PEND_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PEND` writer - Pending"] +pub struct PEND_W<'a> { + w: &'a mut W, +} +impl<'a> PEND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u16 & 0x01) << 15); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&mut self) -> ID_W { + ID_W { w: self } + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&mut self) -> TERR_W { + TERR_W { w: self } + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&mut self) -> TCMPL_W { + TCMPL_W { w: self } + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&mut self) -> SUSP_W { + SUSP_W { w: self } + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&mut self) -> FERR_W { + FERR_W { w: self } + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&mut self) -> BUSY_W { + BUSY_W { w: self } + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&mut self) -> PEND_W { + PEND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/intstatus.rs b/src/dmac/intstatus.rs new file mode 100644 index 0000000..40a10a8 --- /dev/null +++ b/src/dmac/intstatus.rs @@ -0,0 +1,261 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R<INTSTATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTSTATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTSTATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTSTATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub struct CHINT0_R(crate::FieldReader<bool, bool>); +impl CHINT0_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub struct CHINT1_R(crate::FieldReader<bool, bool>); +impl CHINT1_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub struct CHINT2_R(crate::FieldReader<bool, bool>); +impl CHINT2_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub struct CHINT3_R(crate::FieldReader<bool, bool>); +impl CHINT3_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub struct CHINT4_R(crate::FieldReader<bool, bool>); +impl CHINT4_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT4_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub struct CHINT5_R(crate::FieldReader<bool, bool>); +impl CHINT5_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT5_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub struct CHINT6_R(crate::FieldReader<bool, bool>); +impl CHINT6_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT6_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub struct CHINT7_R(crate::FieldReader<bool, bool>); +impl CHINT7_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT7_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub struct CHINT8_R(crate::FieldReader<bool, bool>); +impl CHINT8_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT8_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub struct CHINT9_R(crate::FieldReader<bool, bool>); +impl CHINT9_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT9_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub struct CHINT10_R(crate::FieldReader<bool, bool>); +impl CHINT10_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT10_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub struct CHINT11_R(crate::FieldReader<bool, bool>); +impl CHINT11_R { + pub(crate) fn new(bits: bool) -> Self { + CHINT11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CHINT11_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/pendch.rs b/src/dmac/pendch.rs new file mode 100644 index 0000000..b6314af --- /dev/null +++ b/src/dmac/pendch.rs @@ -0,0 +1,261 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R<PENDCH_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<PENDCH_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<PENDCH_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<PENDCH_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub struct PENDCH0_R(crate::FieldReader<bool, bool>); +impl PENDCH0_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub struct PENDCH1_R(crate::FieldReader<bool, bool>); +impl PENDCH1_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub struct PENDCH2_R(crate::FieldReader<bool, bool>); +impl PENDCH2_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub struct PENDCH3_R(crate::FieldReader<bool, bool>); +impl PENDCH3_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub struct PENDCH4_R(crate::FieldReader<bool, bool>); +impl PENDCH4_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH4_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub struct PENDCH5_R(crate::FieldReader<bool, bool>); +impl PENDCH5_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH5_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub struct PENDCH6_R(crate::FieldReader<bool, bool>); +impl PENDCH6_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH6_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub struct PENDCH7_R(crate::FieldReader<bool, bool>); +impl PENDCH7_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH7_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub struct PENDCH8_R(crate::FieldReader<bool, bool>); +impl PENDCH8_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH8_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub struct PENDCH9_R(crate::FieldReader<bool, bool>); +impl PENDCH9_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH9_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub struct PENDCH10_R(crate::FieldReader<bool, bool>); +impl PENDCH10_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH10_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub struct PENDCH11_R(crate::FieldReader<bool, bool>); +impl PENDCH11_R { + pub(crate) fn new(bits: bool) -> Self { + PENDCH11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PENDCH11_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/prictrl0.rs b/src/dmac/prictrl0.rs new file mode 100644 index 0000000..a5b7cd9 --- /dev/null +++ b/src/dmac/prictrl0.rs @@ -0,0 +1,441 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R<PRICTRL0_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<PRICTRL0_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<PRICTRL0_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<PRICTRL0_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W<PRICTRL0_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<PRICTRL0_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<PRICTRL0_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<PRICTRL0_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub struct LVLPRI0_R(crate::FieldReader<u8, u8>); +impl LVLPRI0_R { + pub(crate) fn new(bits: u8) -> Self { + LVLPRI0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI0_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub struct LVLPRI0_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI0_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); + self.w + } +} +#[doc = "Level 0 Round-Robin Scheduling Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum RRLVLEN0_A { + #[doc = "0: Static arbitration scheme for channels with level 3 priority"] + STATIC_LVL = 0, + #[doc = "1: Round-robin arbitration scheme for channels with level 3 priority"] + ROUND_ROBIN_LVL = 1, +} +impl From<RRLVLEN0_A> for bool { + #[inline(always)] + fn from(variant: RRLVLEN0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_R(crate::FieldReader<bool, RRLVLEN0_A>); +impl RRLVLEN0_R { + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN0_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RRLVLEN0_A { + match self.bits { + false => RRLVLEN0_A::STATIC_LVL, + true => RRLVLEN0_A::ROUND_ROBIN_LVL, + } + } + #[doc = "Checks if the value of the field is `STATIC_LVL`"] + #[inline(always)] + pub fn is_static_lvl(&self) -> bool { + **self == RRLVLEN0_A::STATIC_LVL + } + #[doc = "Checks if the value of the field is `ROUND_ROBIN_LVL`"] + #[inline(always)] + pub fn is_round_robin_lvl(&self) -> bool { + **self == RRLVLEN0_A::ROUND_ROBIN_LVL + } +} +impl core::ops::Deref for RRLVLEN0_R { + type Target = crate::FieldReader<bool, RRLVLEN0_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub struct RRLVLEN0_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN0_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: RRLVLEN0_A) -> &'a mut W { + self.bit(variant.into()) + } + #[doc = "Static arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn static_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::STATIC_LVL) + } + #[doc = "Round-robin arbitration scheme for channels with level 3 priority"] + #[inline(always)] + pub fn round_robin_lvl(self) -> &'a mut W { + self.variant(RRLVLEN0_A::ROUND_ROBIN_LVL) + } + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub struct LVLPRI1_R(crate::FieldReader<u8, u8>); +impl LVLPRI1_R { + pub(crate) fn new(bits: u8) -> Self { + LVLPRI1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI1_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub struct LVLPRI1_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI1_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); + self.w + } +} +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_R(crate::FieldReader<bool, bool>); +impl RRLVLEN1_R { + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub struct RRLVLEN1_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub struct LVLPRI2_R(crate::FieldReader<u8, u8>); +impl LVLPRI2_R { + pub(crate) fn new(bits: u8) -> Self { + LVLPRI2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI2_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub struct LVLPRI2_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI2_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_R(crate::FieldReader<bool, bool>); +impl RRLVLEN2_R { + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub struct RRLVLEN2_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub struct LVLPRI3_R(crate::FieldReader<u8, u8>); +impl LVLPRI3_R { + pub(crate) fn new(bits: u8) -> Self { + LVLPRI3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LVLPRI3_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub struct LVLPRI3_W<'a> { + w: &'a mut W, +} +impl<'a> LVLPRI3_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24); + self.w + } +} +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_R(crate::FieldReader<bool, bool>); +impl RRLVLEN3_R { + pub(crate) fn new(bits: bool) -> Self { + RRLVLEN3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RRLVLEN3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub struct RRLVLEN3_W<'a> { + w: &'a mut W, +} +impl<'a> RRLVLEN3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 0x01) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&mut self) -> LVLPRI0_W { + LVLPRI0_W { w: self } + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W { + RRLVLEN0_W { w: self } + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&mut self) -> LVLPRI1_W { + LVLPRI1_W { w: self } + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W { + RRLVLEN1_W { w: self } + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&mut self) -> LVLPRI2_W { + LVLPRI2_W { w: self } + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W { + RRLVLEN2_W { w: self } + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&mut self) -> LVLPRI3_W { + LVLPRI3_W { w: self } + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W { + RRLVLEN3_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/qosctrl.rs b/src/dmac/qosctrl.rs new file mode 100644 index 0000000..44706a5 --- /dev/null +++ b/src/dmac/qosctrl.rs @@ -0,0 +1,399 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R<QOSCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<QOSCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<QOSCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<QOSCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W<QOSCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<QOSCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<QOSCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<QOSCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum WRBQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From<WRBQOS_A> for u8 { + #[inline(always)] + fn from(variant: WRBQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub struct WRBQOS_R(crate::FieldReader<u8, WRBQOS_A>); +impl WRBQOS_R { + pub(crate) fn new(bits: u8) -> Self { + WRBQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOS_A { + match self.bits { + 0 => WRBQOS_A::DISABLE, + 1 => WRBQOS_A::LOW, + 2 => WRBQOS_A::MEDIUM, + 3 => WRBQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == WRBQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == WRBQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == WRBQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == WRBQOS_A::HIGH + } +} +impl core::ops::Deref for WRBQOS_R { + type Target = crate::FieldReader<u8, WRBQOS_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub struct WRBQOS_W<'a> { + w: &'a mut W, +} +impl<'a> WRBQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: WRBQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From<FQOS_A> for u8 { + #[inline(always)] + fn from(variant: FQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub struct FQOS_R(crate::FieldReader<u8, FQOS_A>); +impl FQOS_R { + pub(crate) fn new(bits: u8) -> Self { + FQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOS_A { + match self.bits { + 0 => FQOS_A::DISABLE, + 1 => FQOS_A::LOW, + 2 => FQOS_A::MEDIUM, + 3 => FQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == FQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == FQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == FQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == FQOS_A::HIGH + } +} +impl core::ops::Deref for FQOS_R { + type Target = crate::FieldReader<u8, FQOS_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub struct FQOS_W<'a> { + w: &'a mut W, +} +impl<'a> FQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 2)) | ((value as u8 & 0x03) << 2); + self.w + } +} +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DQOS_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From<DQOS_A> for u8 { + #[inline(always)] + fn from(variant: DQOS_A) -> Self { + variant as _ + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub struct DQOS_R(crate::FieldReader<u8, DQOS_A>); +impl DQOS_R { + pub(crate) fn new(bits: u8) -> Self { + DQOS_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOS_A { + match self.bits { + 0 => DQOS_A::DISABLE, + 1 => DQOS_A::LOW, + 2 => DQOS_A::MEDIUM, + 3 => DQOS_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == DQOS_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + **self == DQOS_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + **self == DQOS_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + **self == DQOS_A::HIGH + } +} +impl core::ops::Deref for DQOS_R { + type Target = crate::FieldReader<u8, DQOS_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub struct DQOS_W<'a> { + w: &'a mut W, +} +impl<'a> DQOS_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DQOS_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOS_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOS_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOS_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOS_A::HIGH) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u8 & 0x03) << 4); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new(((self.bits >> 2) & 0x03) as u8) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new(((self.bits >> 4) & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&mut self) -> WRBQOS_W { + WRBQOS_W { w: self } + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&mut self) -> FQOS_W { + FQOS_W { w: self } + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&mut self) -> DQOS_W { + DQOS_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x2a + } +} diff --git a/src/dmac/swtrigctrl.rs b/src/dmac/swtrigctrl.rs new file mode 100644 index 0000000..2ff5355 --- /dev/null +++ b/src/dmac/swtrigctrl.rs @@ -0,0 +1,618 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R<SWTRIGCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<SWTRIGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<SWTRIGCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<SWTRIGCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W<SWTRIGCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<SWTRIGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<SWTRIGCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<SWTRIGCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub struct SWTRIG0_R(crate::FieldReader<bool, bool>); +impl SWTRIG0_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG0_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG0_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub struct SWTRIG0_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG0_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub struct SWTRIG1_R(crate::FieldReader<bool, bool>); +impl SWTRIG1_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG1_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG1_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub struct SWTRIG1_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG1_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub struct SWTRIG2_R(crate::FieldReader<bool, bool>); +impl SWTRIG2_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG2_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG2_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub struct SWTRIG2_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG2_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub struct SWTRIG3_R(crate::FieldReader<bool, bool>); +impl SWTRIG3_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG3_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG3_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub struct SWTRIG3_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG3_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub struct SWTRIG4_R(crate::FieldReader<bool, bool>); +impl SWTRIG4_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG4_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG4_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub struct SWTRIG4_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG4_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub struct SWTRIG5_R(crate::FieldReader<bool, bool>); +impl SWTRIG5_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG5_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG5_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub struct SWTRIG5_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG5_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub struct SWTRIG6_R(crate::FieldReader<bool, bool>); +impl SWTRIG6_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG6_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG6_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub struct SWTRIG6_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG6_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub struct SWTRIG7_R(crate::FieldReader<bool, bool>); +impl SWTRIG7_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG7_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG7_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub struct SWTRIG7_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG7_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub struct SWTRIG8_R(crate::FieldReader<bool, bool>); +impl SWTRIG8_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG8_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG8_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub struct SWTRIG8_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG8_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub struct SWTRIG9_R(crate::FieldReader<bool, bool>); +impl SWTRIG9_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG9_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG9_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub struct SWTRIG9_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG9_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub struct SWTRIG10_R(crate::FieldReader<bool, bool>); +impl SWTRIG10_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG10_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG10_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub struct SWTRIG10_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG10_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub struct SWTRIG11_R(crate::FieldReader<bool, bool>); +impl SWTRIG11_R { + pub(crate) fn new(bits: bool) -> Self { + SWTRIG11_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWTRIG11_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub struct SWTRIG11_W<'a> { + w: &'a mut W, +} +impl<'a> SWTRIG11_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&mut self) -> SWTRIG0_W { + SWTRIG0_W { w: self } + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&mut self) -> SWTRIG1_W { + SWTRIG1_W { w: self } + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&mut self) -> SWTRIG2_W { + SWTRIG2_W { w: self } + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&mut self) -> SWTRIG3_W { + SWTRIG3_W { w: self } + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&mut self) -> SWTRIG4_W { + SWTRIG4_W { w: self } + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&mut self) -> SWTRIG5_W { + SWTRIG5_W { w: self } + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&mut self) -> SWTRIG6_W { + SWTRIG6_W { w: self } + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&mut self) -> SWTRIG7_W { + SWTRIG7_W { w: self } + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&mut self) -> SWTRIG8_W { + SWTRIG8_W { w: self } + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&mut self) -> SWTRIG9_W { + SWTRIG9_W { w: self } + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&mut self) -> SWTRIG10_W { + SWTRIG10_W { w: self } + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&mut self) -> SWTRIG11_W { + SWTRIG11_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/dmac/wrbaddr.rs b/src/dmac/wrbaddr.rs new file mode 100644 index 0000000..4b04172 --- /dev/null +++ b/src/dmac/wrbaddr.rs @@ -0,0 +1,102 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R<WRBADDR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<WRBADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<WRBADDR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<WRBADDR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W<WRBADDR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<WRBADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<WRBADDR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<WRBADDR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub struct WRBADDR_R(crate::FieldReader<u32, u32>); +impl WRBADDR_R { + pub(crate) fn new(bits: u32) -> Self { + WRBADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WRBADDR_R { + type Target = crate::FieldReader<u32, u32>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub struct WRBADDR_W<'a> { + w: &'a mut W, +} +impl<'a> WRBADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u32) -> &'a mut W { + self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff); + self.w + } +} +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new((self.bits & 0xffff_ffff) as u32) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&mut self) -> WRBADDR_W { + WRBADDR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} |