diff options
Diffstat (limited to 'src/oscctrl')
| -rw-r--r-- | src/oscctrl/cal48m.rs | 174 | ||||
| -rw-r--r-- | src/oscctrl/cfdpresc.rs | 229 | ||||
| -rw-r--r-- | src/oscctrl/dpllctrla.rs | 204 | ||||
| -rw-r--r-- | src/oscctrl/dpllctrlb.rs | 573 | ||||
| -rw-r--r-- | src/oscctrl/dpllpresc.rs | 164 | ||||
| -rw-r--r-- | src/oscctrl/dpllratio.rs | 138 | ||||
| -rw-r--r-- | src/oscctrl/dpllstatus.rs | 71 | ||||
| -rw-r--r-- | src/oscctrl/dpllsyncbusy.rs | 90 | ||||
| -rw-r--r-- | src/oscctrl/evctrl.rs | 112 | ||||
| -rw-r--r-- | src/oscctrl/intenclr.rs | 388 | ||||
| -rw-r--r-- | src/oscctrl/intenset.rs | 388 | ||||
| -rw-r--r-- | src/oscctrl/intflag.rs | 388 | ||||
| -rw-r--r-- | src/oscctrl/osc48mctrl.rs | 204 | ||||
| -rw-r--r-- | src/oscctrl/osc48mdiv.rs | 333 | ||||
| -rw-r--r-- | src/oscctrl/osc48mstup.rs | 229 | ||||
| -rw-r--r-- | src/oscctrl/osc48msyncbusy.rs | 52 | ||||
| -rw-r--r-- | src/oscctrl/status.rs | 185 | ||||
| -rw-r--r-- | src/oscctrl/xoscctrl.rs | 779 |
18 files changed, 4701 insertions, 0 deletions
diff --git a/src/oscctrl/cal48m.rs b/src/oscctrl/cal48m.rs new file mode 100644 index 0000000..e51d113 --- /dev/null +++ b/src/oscctrl/cal48m.rs @@ -0,0 +1,174 @@ +#[doc = "Register `CAL48M` reader"] +pub struct R(crate::R<CAL48M_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CAL48M_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CAL48M_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CAL48M_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CAL48M` writer"] +pub struct W(crate::W<CAL48M_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CAL48M_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CAL48M_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CAL48M_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `FCAL` reader - Frequency Calibration (48MHz)"] +pub struct FCAL_R(crate::FieldReader<u8, u8>); +impl FCAL_R { + pub(crate) fn new(bits: u8) -> Self { + FCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FCAL_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FCAL` writer - Frequency Calibration (48MHz)"] +pub struct FCAL_W<'a> { + w: &'a mut W, +} +impl<'a> FCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f); + self.w + } +} +#[doc = "Field `FRANGE` reader - Frequency Range (48MHz)"] +pub struct FRANGE_R(crate::FieldReader<u8, u8>); +impl FRANGE_R { + pub(crate) fn new(bits: u8) -> Self { + FRANGE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FRANGE_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FRANGE` writer - Frequency Range (48MHz)"] +pub struct FRANGE_W<'a> { + w: &'a mut W, +} +impl<'a> FRANGE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 8)) | ((value as u32 & 0x03) << 8); + self.w + } +} +#[doc = "Field `TCAL` reader - Temperature Calibration (48MHz)"] +pub struct TCAL_R(crate::FieldReader<u8, u8>); +impl TCAL_R { + pub(crate) fn new(bits: u8) -> Self { + TCAL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCAL_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCAL` writer - Temperature Calibration (48MHz)"] +pub struct TCAL_W<'a> { + w: &'a mut W, +} +impl<'a> TCAL_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x3f << 16)) | ((value as u32 & 0x3f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&self) -> FCAL_R { + FCAL_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&self) -> FRANGE_R { + FRANGE_R::new(((self.bits >> 8) & 0x03) as u8) + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&self) -> TCAL_R { + TCAL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Frequency Calibration (48MHz)"] + #[inline(always)] + pub fn fcal(&mut self) -> FCAL_W { + FCAL_W { w: self } + } + #[doc = "Bits 8:9 - Frequency Range (48MHz)"] + #[inline(always)] + pub fn frange(&mut self) -> FRANGE_W { + FRANGE_W { w: self } + } + #[doc = "Bits 16:21 - Temperature Calibration (48MHz)"] + #[inline(always)] + pub fn tcal(&mut self) -> TCAL_W { + TCAL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Oscillator Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cal48m](index.html) module"] +pub struct CAL48M_SPEC; +impl crate::RegisterSpec for CAL48M_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cal48m::R](R) reader structure"] +impl crate::Readable for CAL48M_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cal48m::W](W) writer structure"] +impl crate::Writable for CAL48M_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CAL48M to value 0"] +impl crate::Resettable for CAL48M_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/cfdpresc.rs b/src/oscctrl/cfdpresc.rs new file mode 100644 index 0000000..7f0a995 --- /dev/null +++ b/src/oscctrl/cfdpresc.rs @@ -0,0 +1,229 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R<CFDPRESC_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CFDPRESC_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CFDPRESC_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CFDPRESC_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W<CFDPRESC_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CFDPRESC_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CFDPRESC_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CFDPRESC_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Clock Failure Detector Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CFDPRESC_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 12 MHz"] + DIV4 = 2, + #[doc = "3: 6 MHz"] + DIV8 = 3, + #[doc = "4: 3 MHz"] + DIV16 = 4, + #[doc = "5: 1.5 MHz"] + DIV32 = 5, + #[doc = "6: 0.75 MHz"] + DIV64 = 6, + #[doc = "7: 0.3125 MHz"] + DIV128 = 7, +} +impl From<CFDPRESC_A> for u8 { + #[inline(always)] + fn from(variant: CFDPRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_R(crate::FieldReader<u8, CFDPRESC_A>); +impl CFDPRESC_R { + pub(crate) fn new(bits: u8) -> Self { + CFDPRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CFDPRESC_A { + match self.bits { + 0 => CFDPRESC_A::DIV1, + 1 => CFDPRESC_A::DIV2, + 2 => CFDPRESC_A::DIV4, + 3 => CFDPRESC_A::DIV8, + 4 => CFDPRESC_A::DIV16, + 5 => CFDPRESC_A::DIV32, + 6 => CFDPRESC_A::DIV64, + 7 => CFDPRESC_A::DIV128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CFDPRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CFDPRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CFDPRESC_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CFDPRESC_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CFDPRESC_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CFDPRESC_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CFDPRESC_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CFDPRESC_A::DIV128 + } +} +impl core::ops::Deref for CFDPRESC_R { + type Target = crate::FieldReader<u8, CFDPRESC_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub struct CFDPRESC_W<'a> { + w: &'a mut W, +} +impl<'a> CFDPRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CFDPRESC_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV2) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV4) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV8) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV16) + } + #[doc = "1.5 MHz"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV32) + } + #[doc = "0.75 MHz"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV64) + } + #[doc = "0.3125 MHz"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CFDPRESC_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&mut self) -> CFDPRESC_W { + CFDPRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/dpllctrla.rs b/src/oscctrl/dpllctrla.rs new file mode 100644 index 0000000..08448b2 --- /dev/null +++ b/src/oscctrl/dpllctrla.rs @@ -0,0 +1,204 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R<DPLLCTRLA_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLCTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLCTRLA_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLCTRLA_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W<DPLLCTRLA_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DPLLCTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DPLLCTRLA_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DPLLCTRLA_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub struct ONDEMAND_R(crate::FieldReader<bool, bool>); +impl ONDEMAND_R { + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} diff --git a/src/oscctrl/dpllctrlb.rs b/src/oscctrl/dpllctrlb.rs new file mode 100644 index 0000000..6ba8999 --- /dev/null +++ b/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,573 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R<DPLLCTRLB_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLCTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLCTRLB_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLCTRLB_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W<DPLLCTRLB_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DPLLCTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DPLLCTRLB_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DPLLCTRLB_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum FILTER_A { + #[doc = "0: Default filter mode"] + DEFAULT = 0, + #[doc = "1: Low bandwidth filter"] + LBFILT = 1, + #[doc = "2: High bandwidth filter"] + HBFILT = 2, + #[doc = "3: High damping filter"] + HDFILT = 3, +} +impl From<FILTER_A> for u8 { + #[inline(always)] + fn from(variant: FILTER_A) -> Self { + variant as _ + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub struct FILTER_R(crate::FieldReader<u8, FILTER_A>); +impl FILTER_R { + pub(crate) fn new(bits: u8) -> Self { + FILTER_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FILTER_A { + match self.bits { + 0 => FILTER_A::DEFAULT, + 1 => FILTER_A::LBFILT, + 2 => FILTER_A::HBFILT, + 3 => FILTER_A::HDFILT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == FILTER_A::DEFAULT + } + #[doc = "Checks if the value of the field is `LBFILT`"] + #[inline(always)] + pub fn is_lbfilt(&self) -> bool { + **self == FILTER_A::LBFILT + } + #[doc = "Checks if the value of the field is `HBFILT`"] + #[inline(always)] + pub fn is_hbfilt(&self) -> bool { + **self == FILTER_A::HBFILT + } + #[doc = "Checks if the value of the field is `HDFILT`"] + #[inline(always)] + pub fn is_hdfilt(&self) -> bool { + **self == FILTER_A::HDFILT + } +} +impl core::ops::Deref for FILTER_R { + type Target = crate::FieldReader<u8, FILTER_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub struct FILTER_W<'a> { + w: &'a mut W, +} +impl<'a> FILTER_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FILTER_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Default filter mode"] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(FILTER_A::DEFAULT) + } + #[doc = "Low bandwidth filter"] + #[inline(always)] + pub fn lbfilt(self) -> &'a mut W { + self.variant(FILTER_A::LBFILT) + } + #[doc = "High bandwidth filter"] + #[inline(always)] + pub fn hbfilt(self) -> &'a mut W { + self.variant(FILTER_A::HBFILT) + } + #[doc = "High damping filter"] + #[inline(always)] + pub fn hdfilt(self) -> &'a mut W { + self.variant(FILTER_A::HDFILT) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u32 & 0x03); + self.w + } +} +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub struct LPEN_R(crate::FieldReader<bool, bool>); +impl LPEN_R { + pub(crate) fn new(bits: bool) -> Self { + LPEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LPEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub struct LPEN_W<'a> { + w: &'a mut W, +} +impl<'a> LPEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub struct WUF_R(crate::FieldReader<bool, bool>); +impl WUF_R { + pub(crate) fn new(bits: bool) -> Self { + WUF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WUF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub struct WUF_W<'a> { + w: &'a mut W, +} +impl<'a> WUF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Reference Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum REFCLK_A { + #[doc = "0: XOSC32K clock reference"] + XOSC32K = 0, + #[doc = "1: XOSC clock reference"] + XOSC = 1, + #[doc = "2: GCLK clock reference"] + GCLK = 2, +} +impl From<REFCLK_A> for u8 { + #[inline(always)] + fn from(variant: REFCLK_A) -> Self { + variant as _ + } +} +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub struct REFCLK_R(crate::FieldReader<u8, REFCLK_A>); +impl REFCLK_R { + pub(crate) fn new(bits: u8) -> Self { + REFCLK_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<REFCLK_A> { + match self.bits { + 0 => Some(REFCLK_A::XOSC32K), + 1 => Some(REFCLK_A::XOSC), + 2 => Some(REFCLK_A::GCLK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + **self == REFCLK_A::XOSC32K + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + **self == REFCLK_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + **self == REFCLK_A::GCLK + } +} +impl core::ops::Deref for REFCLK_R { + type Target = crate::FieldReader<u8, REFCLK_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub struct REFCLK_W<'a> { + w: &'a mut W, +} +impl<'a> REFCLK_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: REFCLK_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "XOSC32K clock reference"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC32K) + } + #[doc = "XOSC clock reference"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(REFCLK_A::XOSC) + } + #[doc = "GCLK clock reference"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(REFCLK_A::GCLK) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u32 & 0x03) << 4); + self.w + } +} +#[doc = "Lock Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum LTIME_A { + #[doc = "0: No time-out. Automatic lock."] + DEFAULT = 0, + #[doc = "4: Time-out if no lock within 8ms"] + _8MS = 4, + #[doc = "5: Time-out if no lock within 9ms"] + _9MS = 5, + #[doc = "6: Time-out if no lock within 10ms"] + _10MS = 6, + #[doc = "7: Time-out if no lock within 11ms"] + _11MS = 7, +} +impl From<LTIME_A> for u8 { + #[inline(always)] + fn from(variant: LTIME_A) -> Self { + variant as _ + } +} +#[doc = "Field `LTIME` reader - Lock Time"] +pub struct LTIME_R(crate::FieldReader<u8, LTIME_A>); +impl LTIME_R { + pub(crate) fn new(bits: u8) -> Self { + LTIME_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<LTIME_A> { + match self.bits { + 0 => Some(LTIME_A::DEFAULT), + 4 => Some(LTIME_A::_8MS), + 5 => Some(LTIME_A::_9MS), + 6 => Some(LTIME_A::_10MS), + 7 => Some(LTIME_A::_11MS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEFAULT`"] + #[inline(always)] + pub fn is_default(&self) -> bool { + **self == LTIME_A::DEFAULT + } + #[doc = "Checks if the value of the field is `_8MS`"] + #[inline(always)] + pub fn is_8ms(&self) -> bool { + **self == LTIME_A::_8MS + } + #[doc = "Checks if the value of the field is `_9MS`"] + #[inline(always)] + pub fn is_9ms(&self) -> bool { + **self == LTIME_A::_9MS + } + #[doc = "Checks if the value of the field is `_10MS`"] + #[inline(always)] + pub fn is_10ms(&self) -> bool { + **self == LTIME_A::_10MS + } + #[doc = "Checks if the value of the field is `_11MS`"] + #[inline(always)] + pub fn is_11ms(&self) -> bool { + **self == LTIME_A::_11MS + } +} +impl core::ops::Deref for LTIME_R { + type Target = crate::FieldReader<u8, LTIME_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LTIME` writer - Lock Time"] +pub struct LTIME_W<'a> { + w: &'a mut W, +} +impl<'a> LTIME_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: LTIME_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "No time-out. Automatic lock."] + #[inline(always)] + pub fn default(self) -> &'a mut W { + self.variant(LTIME_A::DEFAULT) + } + #[doc = "Time-out if no lock within 8ms"] + #[inline(always)] + pub fn _8ms(self) -> &'a mut W { + self.variant(LTIME_A::_8MS) + } + #[doc = "Time-out if no lock within 9ms"] + #[inline(always)] + pub fn _9ms(self) -> &'a mut W { + self.variant(LTIME_A::_9MS) + } + #[doc = "Time-out if no lock within 10ms"] + #[inline(always)] + pub fn _10ms(self) -> &'a mut W { + self.variant(LTIME_A::_10MS) + } + #[doc = "Time-out if no lock within 11ms"] + #[inline(always)] + pub fn _11ms(self) -> &'a mut W { + self.variant(LTIME_A::_11MS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8); + self.w + } +} +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub struct LBYPASS_R(crate::FieldReader<bool, bool>); +impl LBYPASS_R { + pub(crate) fn new(bits: bool) -> Self { + LBYPASS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LBYPASS_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub struct LBYPASS_W<'a> { + w: &'a mut W, +} +impl<'a> LBYPASS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `DIV` reader - Clock Divider"] +pub struct DIV_R(crate::FieldReader<u16, u16>); +impl DIV_R { + pub(crate) fn new(bits: u16) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader<u16, u16>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - Clock Divider"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07ff << 16)) | ((value as u32 & 0x07ff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 0x03) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&mut self) -> FILTER_W { + FILTER_W { w: self } + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&mut self) -> LPEN_W { + LPEN_W { w: self } + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&mut self) -> WUF_W { + WUF_W { w: self } + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&mut self) -> REFCLK_W { + REFCLK_W { w: self } + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&mut self) -> LTIME_W { + LTIME_W { w: self } + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&mut self) -> LBYPASS_W { + LBYPASS_W { w: self } + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/dpllpresc.rs b/src/oscctrl/dpllpresc.rs new file mode 100644 index 0000000..8dcc427 --- /dev/null +++ b/src/oscctrl/dpllpresc.rs @@ -0,0 +1,164 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R<DPLLPRESC_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLPRESC_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLPRESC_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLPRESC_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W<DPLLPRESC_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DPLLPRESC_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DPLLPRESC_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DPLLPRESC_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum PRESC_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From<PRESC_A> for u8 { + #[inline(always)] + fn from(variant: PRESC_A) -> Self { + variant as _ + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub struct PRESC_R(crate::FieldReader<u8, PRESC_A>); +impl PRESC_R { + pub(crate) fn new(bits: u8) -> Self { + PRESC_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<PRESC_A> { + match self.bits { + 0 => Some(PRESC_A::DIV1), + 1 => Some(PRESC_A::DIV2), + 2 => Some(PRESC_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == PRESC_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == PRESC_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == PRESC_A::DIV4 + } +} +impl core::ops::Deref for PRESC_R { + type Target = crate::FieldReader<u8, PRESC_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub struct PRESC_W<'a> { + w: &'a mut W, +} +impl<'a> PRESC_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: PRESC_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESC_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESC_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESC_A::DIV4) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03); + self.w + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new((self.bits & 0x03) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&mut self) -> PRESC_W { + PRESC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/dpllratio.rs b/src/oscctrl/dpllratio.rs new file mode 100644 index 0000000..90a2c48 --- /dev/null +++ b/src/oscctrl/dpllratio.rs @@ -0,0 +1,138 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R<DPLLRATIO_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLRATIO_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLRATIO_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLRATIO_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W<DPLLRATIO_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DPLLRATIO_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DPLLRATIO_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DPLLRATIO_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub struct LDR_R(crate::FieldReader<u16, u16>); +impl LDR_R { + pub(crate) fn new(bits: u16) -> Self { + LDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDR_R { + type Target = crate::FieldReader<u16, u16>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub struct LDR_W<'a> { + w: &'a mut W, +} +impl<'a> LDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0fff) | (value as u32 & 0x0fff); + self.w + } +} +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_R(crate::FieldReader<u8, u8>); +impl LDRFRAC_R { + pub(crate) fn new(bits: u8) -> Self { + LDRFRAC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LDRFRAC_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub struct LDRFRAC_W<'a> { + w: &'a mut W, +} +impl<'a> LDRFRAC_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 16)) | ((value as u32 & 0x0f) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&mut self) -> LDR_W { + LDR_W { w: self } + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&mut self) -> LDRFRAC_W { + LDRFRAC_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/dpllstatus.rs b/src/oscctrl/dpllstatus.rs new file mode 100644 index 0000000..c375518 --- /dev/null +++ b/src/oscctrl/dpllstatus.rs @@ -0,0 +1,71 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R<DPLLSTATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLSTATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLSTATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLSTATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub struct LOCK_R(crate::FieldReader<bool, bool>); +impl LOCK_R { + pub(crate) fn new(bits: bool) -> Self { + LOCK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOCK_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub struct CLKRDY_R(crate::FieldReader<bool, bool>); +impl CLKRDY_R { + pub(crate) fn new(bits: bool) -> Self { + CLKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/dpllsyncbusy.rs b/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 0000000..bd65929 --- /dev/null +++ b/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,90 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R<DPLLSYNCBUSY_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DPLLSYNCBUSY_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DPLLSYNCBUSY_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DPLLSYNCBUSY_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub struct DPLLRATIO_R(crate::FieldReader<bool, bool>); +impl DPLLRATIO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLRATIO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLRATIO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub struct DPLLPRESC_R(crate::FieldReader<bool, bool>); +impl DPLLPRESC_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLPRESC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLPRESC_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 0x01) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/evctrl.rs b/src/oscctrl/evctrl.rs new file mode 100644 index 0000000..bd47766 --- /dev/null +++ b/src/oscctrl/evctrl.rs @@ -0,0 +1,112 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R<EVCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<EVCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<EVCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<EVCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W<EVCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<EVCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<EVCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<EVCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_R(crate::FieldReader<bool, bool>); +impl CFDEO_R { + pub(crate) fn new(bits: bool) -> Self { + CFDEO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub struct CFDEO_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&mut self) -> CFDEO_W { + CFDEO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/intenclr.rs b/src/oscctrl/intenclr.rs new file mode 100644 index 0000000..f489fb7 --- /dev/null +++ b/src/oscctrl/intenclr.rs @@ -0,0 +1,388 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R<INTENCLR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENCLR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENCLR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W<INTENCLR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENCLR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENCLR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader<bool, bool>); +impl XOSCRDY_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader<bool, bool>); +impl XOSCFAIL_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader<bool, bool>); +impl OSC48MRDY_R { + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader<bool, bool>); +impl DPLLLCKR_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader<bool, bool>); +impl DPLLLCKF_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader<bool, bool>); +impl DPLLLTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader<bool, bool>); +impl DPLLLDRTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/intenset.rs b/src/oscctrl/intenset.rs new file mode 100644 index 0000000..69d1ae4 --- /dev/null +++ b/src/oscctrl/intenset.rs @@ -0,0 +1,388 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R<INTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W<INTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_R(crate::FieldReader<bool, bool>); +impl XOSCRDY_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_R(crate::FieldReader<bool, bool>); +impl XOSCFAIL_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_R(crate::FieldReader<bool, bool>); +impl OSC48MRDY_R { + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready Interrupt Enable"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_R(crate::FieldReader<bool, bool>); +impl DPLLLCKR_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_R(crate::FieldReader<bool, bool>); +impl DPLLLCKF_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_R(crate::FieldReader<bool, bool>); +impl DPLLLTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_R(crate::FieldReader<bool, bool>); +impl DPLLLDRTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/intflag.rs b/src/oscctrl/intflag.rs new file mode 100644 index 0000000..932f015 --- /dev/null +++ b/src/oscctrl/intflag.rs @@ -0,0 +1,388 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R<INTFLAG_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTFLAG_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTFLAG_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W<INTFLAG_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTFLAG_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTFLAG_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader<bool, bool>); +impl XOSCRDY_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub struct XOSCRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader<bool, bool>); +impl XOSCFAIL_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> XOSCFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader<bool, bool>); +impl OSC48MRDY_R { + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` writer - OSC48M Ready"] +pub struct OSC48MRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC48MRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader<bool, bool>); +impl DPLLLCKR_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub struct DPLLLCKR_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader<bool, bool>); +impl DPLLLCKF_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub struct DPLLLCKF_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLCKF_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub struct DPLLLTO_R(crate::FieldReader<bool, bool>); +impl DPLLLTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub struct DPLLLTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader<bool, bool>); +impl DPLLLDRTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub struct DPLLLDRTO_W<'a> { + w: &'a mut W, +} +impl<'a> DPLLLDRTO_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&mut self) -> XOSCRDY_W { + XOSCRDY_W { w: self } + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&mut self) -> XOSCFAIL_W { + XOSCFAIL_W { w: self } + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&mut self) -> OSC48MRDY_W { + OSC48MRDY_W { w: self } + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&mut self) -> DPLLLCKR_W { + DPLLLCKR_W { w: self } + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&mut self) -> DPLLLCKF_W { + DPLLLCKF_W { w: self } + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&mut self) -> DPLLLTO_W { + DPLLLTO_W { w: self } + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W { + DPLLLDRTO_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/osc48mctrl.rs b/src/oscctrl/osc48mctrl.rs new file mode 100644 index 0000000..d388ccd --- /dev/null +++ b/src/oscctrl/osc48mctrl.rs @@ -0,0 +1,204 @@ +#[doc = "Register `OSC48MCTRL` reader"] +pub struct R(crate::R<OSC48MCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<OSC48MCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<OSC48MCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<OSC48MCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MCTRL` writer"] +pub struct W(crate::W<OSC48MCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<OSC48MCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<OSC48MCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<OSC48MCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader<bool, bool>); +impl ONDEMAND_R { + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "48MHz Internal Oscillator (OSC48M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mctrl](index.html) module"] +pub struct OSC48MCTRL_SPEC; +impl crate::RegisterSpec for OSC48MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mctrl::R](R) reader structure"] +impl crate::Readable for OSC48MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mctrl::W](W) writer structure"] +impl crate::Writable for OSC48MCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MCTRL to value 0x82"] +impl crate::Resettable for OSC48MCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x82 + } +} diff --git a/src/oscctrl/osc48mdiv.rs b/src/oscctrl/osc48mdiv.rs new file mode 100644 index 0000000..cc36ded --- /dev/null +++ b/src/oscctrl/osc48mdiv.rs @@ -0,0 +1,333 @@ +#[doc = "Register `OSC48MDIV` reader"] +pub struct R(crate::R<OSC48MDIV_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<OSC48MDIV_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<OSC48MDIV_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<OSC48MDIV_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MDIV` writer"] +pub struct W(crate::W<OSC48MDIV_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<OSC48MDIV_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<OSC48MDIV_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<OSC48MDIV_SPEC>) -> Self { + W(writer) + } +} +#[doc = "OSC48M Division Factor\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum DIV_A { + #[doc = "0: 48 MHz"] + DIV1 = 0, + #[doc = "1: 24 MHz"] + DIV2 = 1, + #[doc = "2: 16 MHz"] + DIV3 = 2, + #[doc = "3: 12 MHz"] + DIV4 = 3, + #[doc = "4: 9.6 MHz"] + DIV5 = 4, + #[doc = "5: 8 MHz"] + DIV6 = 5, + #[doc = "6: 6.86 MHz"] + DIV7 = 6, + #[doc = "7: 6 MHz"] + DIV8 = 7, + #[doc = "8: 5.33 MHz"] + DIV9 = 8, + #[doc = "9: 4.8 MHz"] + DIV10 = 9, + #[doc = "10: 4.36 MHz"] + DIV11 = 10, + #[doc = "11: 4 MHz"] + DIV12 = 11, + #[doc = "12: 3.69 MHz"] + DIV13 = 12, + #[doc = "13: 3.43 MHz"] + DIV14 = 13, + #[doc = "14: 3.2 MHz"] + DIV15 = 14, + #[doc = "15: 3 MHz"] + DIV16 = 15, +} +impl From<DIV_A> for u8 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `DIV` reader - OSC48M Division Factor"] +pub struct DIV_R(crate::FieldReader<u8, DIV_A>); +impl DIV_R { + pub(crate) fn new(bits: u8) -> Self { + DIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DIV_A { + match self.bits { + 0 => DIV_A::DIV1, + 1 => DIV_A::DIV2, + 2 => DIV_A::DIV3, + 3 => DIV_A::DIV4, + 4 => DIV_A::DIV5, + 5 => DIV_A::DIV6, + 6 => DIV_A::DIV7, + 7 => DIV_A::DIV8, + 8 => DIV_A::DIV9, + 9 => DIV_A::DIV10, + 10 => DIV_A::DIV11, + 11 => DIV_A::DIV12, + 12 => DIV_A::DIV13, + 13 => DIV_A::DIV14, + 14 => DIV_A::DIV15, + 15 => DIV_A::DIV16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == DIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == DIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV3`"] + #[inline(always)] + pub fn is_div3(&self) -> bool { + **self == DIV_A::DIV3 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == DIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV5`"] + #[inline(always)] + pub fn is_div5(&self) -> bool { + **self == DIV_A::DIV5 + } + #[doc = "Checks if the value of the field is `DIV6`"] + #[inline(always)] + pub fn is_div6(&self) -> bool { + **self == DIV_A::DIV6 + } + #[doc = "Checks if the value of the field is `DIV7`"] + #[inline(always)] + pub fn is_div7(&self) -> bool { + **self == DIV_A::DIV7 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == DIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV9`"] + #[inline(always)] + pub fn is_div9(&self) -> bool { + **self == DIV_A::DIV9 + } + #[doc = "Checks if the value of the field is `DIV10`"] + #[inline(always)] + pub fn is_div10(&self) -> bool { + **self == DIV_A::DIV10 + } + #[doc = "Checks if the value of the field is `DIV11`"] + #[inline(always)] + pub fn is_div11(&self) -> bool { + **self == DIV_A::DIV11 + } + #[doc = "Checks if the value of the field is `DIV12`"] + #[inline(always)] + pub fn is_div12(&self) -> bool { + **self == DIV_A::DIV12 + } + #[doc = "Checks if the value of the field is `DIV13`"] + #[inline(always)] + pub fn is_div13(&self) -> bool { + **self == DIV_A::DIV13 + } + #[doc = "Checks if the value of the field is `DIV14`"] + #[inline(always)] + pub fn is_div14(&self) -> bool { + **self == DIV_A::DIV14 + } + #[doc = "Checks if the value of the field is `DIV15`"] + #[inline(always)] + pub fn is_div15(&self) -> bool { + **self == DIV_A::DIV15 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == DIV_A::DIV16 + } +} +impl core::ops::Deref for DIV_R { + type Target = crate::FieldReader<u8, DIV_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIV` writer - OSC48M Division Factor"] +pub struct DIV_W<'a> { + w: &'a mut W, +} +impl<'a> DIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: DIV_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "48 MHz"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(DIV_A::DIV1) + } + #[doc = "24 MHz"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DIV_A::DIV2) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn div3(self) -> &'a mut W { + self.variant(DIV_A::DIV3) + } + #[doc = "12 MHz"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DIV_A::DIV4) + } + #[doc = "9.6 MHz"] + #[inline(always)] + pub fn div5(self) -> &'a mut W { + self.variant(DIV_A::DIV5) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn div6(self) -> &'a mut W { + self.variant(DIV_A::DIV6) + } + #[doc = "6.86 MHz"] + #[inline(always)] + pub fn div7(self) -> &'a mut W { + self.variant(DIV_A::DIV7) + } + #[doc = "6 MHz"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DIV_A::DIV8) + } + #[doc = "5.33 MHz"] + #[inline(always)] + pub fn div9(self) -> &'a mut W { + self.variant(DIV_A::DIV9) + } + #[doc = "4.8 MHz"] + #[inline(always)] + pub fn div10(self) -> &'a mut W { + self.variant(DIV_A::DIV10) + } + #[doc = "4.36 MHz"] + #[inline(always)] + pub fn div11(self) -> &'a mut W { + self.variant(DIV_A::DIV11) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn div12(self) -> &'a mut W { + self.variant(DIV_A::DIV12) + } + #[doc = "3.69 MHz"] + #[inline(always)] + pub fn div13(self) -> &'a mut W { + self.variant(DIV_A::DIV13) + } + #[doc = "3.43 MHz"] + #[inline(always)] + pub fn div14(self) -> &'a mut W { + self.variant(DIV_A::DIV14) + } + #[doc = "3.2 MHz"] + #[inline(always)] + pub fn div15(self) -> &'a mut W { + self.variant(DIV_A::DIV15) + } + #[doc = "3 MHz"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DIV_A::DIV16) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f); + self.w + } +} +impl R { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - OSC48M Division Factor"] + #[inline(always)] + pub fn div(&mut self) -> DIV_W { + DIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mdiv](index.html) module"] +pub struct OSC48MDIV_SPEC; +impl crate::RegisterSpec for OSC48MDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mdiv::R](R) reader structure"] +impl crate::Readable for OSC48MDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mdiv::W](W) writer structure"] +impl crate::Writable for OSC48MDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MDIV to value 0x0b"] +impl crate::Resettable for OSC48MDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0b + } +} diff --git a/src/oscctrl/osc48mstup.rs b/src/oscctrl/osc48mstup.rs new file mode 100644 index 0000000..14d8bce --- /dev/null +++ b/src/oscctrl/osc48mstup.rs @@ -0,0 +1,229 @@ +#[doc = "Register `OSC48MSTUP` reader"] +pub struct R(crate::R<OSC48MSTUP_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<OSC48MSTUP_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<OSC48MSTUP_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<OSC48MSTUP_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `OSC48MSTUP` writer"] +pub struct W(crate::W<OSC48MSTUP_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<OSC48MSTUP_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<OSC48MSTUP_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<OSC48MSTUP_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Startup Time\n\nValue on reset: 7"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 166 ns"] + CYCLE8 = 0, + #[doc = "1: 333 ns"] + CYCLE16 = 1, + #[doc = "2: 667 ns"] + CYCLE32 = 2, + #[doc = "3: 1.333 us"] + CYCLE64 = 3, + #[doc = "4: 2.667 us"] + CYCLE128 = 4, + #[doc = "5: 5.333 us"] + CYCLE256 = 5, + #[doc = "6: 10.667 us"] + CYCLE512 = 6, + #[doc = "7: 21.333 us"] + CYCLE1024 = 7, +} +impl From<STARTUP_A> for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Startup Time"] +pub struct STARTUP_R(crate::FieldReader<u8, STARTUP_A>); +impl STARTUP_R { + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE8, + 1 => STARTUP_A::CYCLE16, + 2 => STARTUP_A::CYCLE32, + 3 => STARTUP_A::CYCLE64, + 4 => STARTUP_A::CYCLE128, + 5 => STARTUP_A::CYCLE256, + 6 => STARTUP_A::CYCLE512, + 7 => STARTUP_A::CYCLE1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader<u8, STARTUP_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Startup Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "166 ns"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "333 ns"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "667 ns"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1.333 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "2.667 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "5.333 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "10.667 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "21.333 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07) | (value as u8 & 0x07); + self.w + } +} +impl R { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x07) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Startup Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "OSC48M Startup Time\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48mstup](index.html) module"] +pub struct OSC48MSTUP_SPEC; +impl crate::RegisterSpec for OSC48MSTUP_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc48mstup::R](R) reader structure"] +impl crate::Readable for OSC48MSTUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc48mstup::W](W) writer structure"] +impl crate::Writable for OSC48MSTUP_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets OSC48MSTUP to value 0x07"] +impl crate::Resettable for OSC48MSTUP_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/src/oscctrl/osc48msyncbusy.rs b/src/oscctrl/osc48msyncbusy.rs new file mode 100644 index 0000000..40aa888 --- /dev/null +++ b/src/oscctrl/osc48msyncbusy.rs @@ -0,0 +1,52 @@ +#[doc = "Register `OSC48MSYNCBUSY` reader"] +pub struct R(crate::R<OSC48MSYNCBUSY_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<OSC48MSYNCBUSY_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<OSC48MSYNCBUSY_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<OSC48MSYNCBUSY_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `OSC48MDIV` reader - OSC48MDIV Synchronization Status"] +pub struct OSC48MDIV_R(crate::FieldReader<bool, bool>); +impl OSC48MDIV_R { + pub(crate) fn new(bits: bool) -> Self { + OSC48MDIV_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MDIV_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 2 - OSC48MDIV Synchronization Status"] + #[inline(always)] + pub fn osc48mdiv(&self) -> OSC48MDIV_R { + OSC48MDIV_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "OSC48M Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc48msyncbusy](index.html) module"] +pub struct OSC48MSYNCBUSY_SPEC; +impl crate::RegisterSpec for OSC48MSYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osc48msyncbusy::R](R) reader structure"] +impl crate::Readable for OSC48MSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets OSC48MSYNCBUSY to value 0"] +impl crate::Resettable for OSC48MSYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/status.rs b/src/oscctrl/status.rs new file mode 100644 index 0000000..24f73a2 --- /dev/null +++ b/src/oscctrl/status.rs @@ -0,0 +1,185 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R<STATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<STATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<STATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<STATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub struct XOSCRDY_R(crate::FieldReader<bool, bool>); +impl XOSCRDY_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub struct XOSCFAIL_R(crate::FieldReader<bool, bool>); +impl XOSCFAIL_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCFAIL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub struct XOSCCKSW_R(crate::FieldReader<bool, bool>); +impl XOSCCKSW_R { + pub(crate) fn new(bits: bool) -> Self { + XOSCCKSW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSCCKSW_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC48MRDY` reader - OSC48M Ready"] +pub struct OSC48MRDY_R(crate::FieldReader<bool, bool>); +impl OSC48MRDY_R { + pub(crate) fn new(bits: bool) -> Self { + OSC48MRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC48MRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub struct DPLLLCKR_R(crate::FieldReader<bool, bool>); +impl DPLLLCKR_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub struct DPLLLCKF_R(crate::FieldReader<bool, bool>); +impl DPLLLCKF_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLCKF_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLCKF_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub struct DPLLTO_R(crate::FieldReader<bool, bool>); +impl DPLLTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub struct DPLLLDRTO_R(crate::FieldReader<bool, bool>); +impl DPLLLDRTO_R { + pub(crate) fn new(bits: bool) -> Self { + DPLLLDRTO_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DPLLLDRTO_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 4 - OSC48M Ready"] + #[inline(always)] + pub fn osc48mrdy(&self) -> OSC48MRDY_R { + OSC48MRDY_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 8 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 11) & 0x01) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/oscctrl/xoscctrl.rs b/src/oscctrl/xoscctrl.rs new file mode 100644 index 0000000..8126768 --- /dev/null +++ b/src/oscctrl/xoscctrl.rs @@ -0,0 +1,779 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R<XOSCCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<XOSCCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<XOSCCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<XOSCCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W<XOSCCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<XOSCCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<XOSCCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<XOSCCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub struct XTALEN_R(crate::FieldReader<bool, bool>); +impl XTALEN_R { + pub(crate) fn new(bits: bool) -> Self { + XTALEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XTALEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub struct XTALEN_W<'a> { + w: &'a mut W, +} +impl<'a> XTALEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_R(crate::FieldReader<bool, bool>); +impl CFDEN_R { + pub(crate) fn new(bits: bool) -> Self { + CFDEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CFDEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detector Enable"] +pub struct CFDEN_W<'a> { + w: &'a mut W, +} +impl<'a> CFDEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub struct SWBEN_R(crate::FieldReader<bool, bool>); +impl SWBEN_R { + pub(crate) fn new(bits: bool) -> Self { + SWBEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWBEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub struct SWBEN_W<'a> { + w: &'a mut W, +} +impl<'a> SWBEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub struct ONDEMAND_R(crate::FieldReader<bool, bool>); +impl ONDEMAND_R { + pub(crate) fn new(bits: bool) -> Self { + ONDEMAND_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ONDEMAND_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub struct ONDEMAND_W<'a> { + w: &'a mut W, +} +impl<'a> ONDEMAND_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Oscillator Gain\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum GAIN_A { + #[doc = "0: 2 MHz"] + GAIN2 = 0, + #[doc = "1: 4 MHz"] + GAIN4 = 1, + #[doc = "2: 8 MHz"] + GAIN8 = 2, + #[doc = "3: 16 MHz"] + GAIN16 = 3, + #[doc = "4: 30 MHz"] + GAIN30 = 4, +} +impl From<GAIN_A> for u8 { + #[inline(always)] + fn from(variant: GAIN_A) -> Self { + variant as _ + } +} +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub struct GAIN_R(crate::FieldReader<u8, GAIN_A>); +impl GAIN_R { + pub(crate) fn new(bits: u8) -> Self { + GAIN_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<GAIN_A> { + match self.bits { + 0 => Some(GAIN_A::GAIN2), + 1 => Some(GAIN_A::GAIN4), + 2 => Some(GAIN_A::GAIN8), + 3 => Some(GAIN_A::GAIN16), + 4 => Some(GAIN_A::GAIN30), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GAIN2`"] + #[inline(always)] + pub fn is_gain2(&self) -> bool { + **self == GAIN_A::GAIN2 + } + #[doc = "Checks if the value of the field is `GAIN4`"] + #[inline(always)] + pub fn is_gain4(&self) -> bool { + **self == GAIN_A::GAIN4 + } + #[doc = "Checks if the value of the field is `GAIN8`"] + #[inline(always)] + pub fn is_gain8(&self) -> bool { + **self == GAIN_A::GAIN8 + } + #[doc = "Checks if the value of the field is `GAIN16`"] + #[inline(always)] + pub fn is_gain16(&self) -> bool { + **self == GAIN_A::GAIN16 + } + #[doc = "Checks if the value of the field is `GAIN30`"] + #[inline(always)] + pub fn is_gain30(&self) -> bool { + **self == GAIN_A::GAIN30 + } +} +impl core::ops::Deref for GAIN_R { + type Target = crate::FieldReader<u8, GAIN_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub struct GAIN_W<'a> { + w: &'a mut W, +} +impl<'a> GAIN_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: GAIN_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "2 MHz"] + #[inline(always)] + pub fn gain2(self) -> &'a mut W { + self.variant(GAIN_A::GAIN2) + } + #[doc = "4 MHz"] + #[inline(always)] + pub fn gain4(self) -> &'a mut W { + self.variant(GAIN_A::GAIN4) + } + #[doc = "8 MHz"] + #[inline(always)] + pub fn gain8(self) -> &'a mut W { + self.variant(GAIN_A::GAIN8) + } + #[doc = "16 MHz"] + #[inline(always)] + pub fn gain16(self) -> &'a mut W { + self.variant(GAIN_A::GAIN16) + } + #[doc = "30 MHz"] + #[inline(always)] + pub fn gain30(self) -> &'a mut W { + self.variant(GAIN_A::GAIN30) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8); + self.w + } +} +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub struct AMPGC_R(crate::FieldReader<bool, bool>); +impl AMPGC_R { + pub(crate) fn new(bits: bool) -> Self { + AMPGC_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AMPGC_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub struct AMPGC_W<'a> { + w: &'a mut W, +} +impl<'a> AMPGC_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u16 & 0x01) << 11); + self.w + } +} +#[doc = "Start-Up Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum STARTUP_A { + #[doc = "0: 31 us"] + CYCLE1 = 0, + #[doc = "1: 61 us"] + CYCLE2 = 1, + #[doc = "2: 122 us"] + CYCLE4 = 2, + #[doc = "3: 244 us"] + CYCLE8 = 3, + #[doc = "4: 488 us"] + CYCLE16 = 4, + #[doc = "5: 977 us"] + CYCLE32 = 5, + #[doc = "6: 1953 us"] + CYCLE64 = 6, + #[doc = "7: 3906 us"] + CYCLE128 = 7, + #[doc = "8: 7813 us"] + CYCLE256 = 8, + #[doc = "9: 15625 us"] + CYCLE512 = 9, + #[doc = "10: 31250 us"] + CYCLE1024 = 10, + #[doc = "11: 62500 us"] + CYCLE2048 = 11, + #[doc = "12: 125000 us"] + CYCLE4096 = 12, + #[doc = "13: 250000 us"] + CYCLE8192 = 13, + #[doc = "14: 500000 us"] + CYCLE16384 = 14, + #[doc = "15: 1000000 us"] + CYCLE32768 = 15, +} +impl From<STARTUP_A> for u8 { + #[inline(always)] + fn from(variant: STARTUP_A) -> Self { + variant as _ + } +} +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub struct STARTUP_R(crate::FieldReader<u8, STARTUP_A>); +impl STARTUP_R { + pub(crate) fn new(bits: u8) -> Self { + STARTUP_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> STARTUP_A { + match self.bits { + 0 => STARTUP_A::CYCLE1, + 1 => STARTUP_A::CYCLE2, + 2 => STARTUP_A::CYCLE4, + 3 => STARTUP_A::CYCLE8, + 4 => STARTUP_A::CYCLE16, + 5 => STARTUP_A::CYCLE32, + 6 => STARTUP_A::CYCLE64, + 7 => STARTUP_A::CYCLE128, + 8 => STARTUP_A::CYCLE256, + 9 => STARTUP_A::CYCLE512, + 10 => STARTUP_A::CYCLE1024, + 11 => STARTUP_A::CYCLE2048, + 12 => STARTUP_A::CYCLE4096, + 13 => STARTUP_A::CYCLE8192, + 14 => STARTUP_A::CYCLE16384, + 15 => STARTUP_A::CYCLE32768, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CYCLE1`"] + #[inline(always)] + pub fn is_cycle1(&self) -> bool { + **self == STARTUP_A::CYCLE1 + } + #[doc = "Checks if the value of the field is `CYCLE2`"] + #[inline(always)] + pub fn is_cycle2(&self) -> bool { + **self == STARTUP_A::CYCLE2 + } + #[doc = "Checks if the value of the field is `CYCLE4`"] + #[inline(always)] + pub fn is_cycle4(&self) -> bool { + **self == STARTUP_A::CYCLE4 + } + #[doc = "Checks if the value of the field is `CYCLE8`"] + #[inline(always)] + pub fn is_cycle8(&self) -> bool { + **self == STARTUP_A::CYCLE8 + } + #[doc = "Checks if the value of the field is `CYCLE16`"] + #[inline(always)] + pub fn is_cycle16(&self) -> bool { + **self == STARTUP_A::CYCLE16 + } + #[doc = "Checks if the value of the field is `CYCLE32`"] + #[inline(always)] + pub fn is_cycle32(&self) -> bool { + **self == STARTUP_A::CYCLE32 + } + #[doc = "Checks if the value of the field is `CYCLE64`"] + #[inline(always)] + pub fn is_cycle64(&self) -> bool { + **self == STARTUP_A::CYCLE64 + } + #[doc = "Checks if the value of the field is `CYCLE128`"] + #[inline(always)] + pub fn is_cycle128(&self) -> bool { + **self == STARTUP_A::CYCLE128 + } + #[doc = "Checks if the value of the field is `CYCLE256`"] + #[inline(always)] + pub fn is_cycle256(&self) -> bool { + **self == STARTUP_A::CYCLE256 + } + #[doc = "Checks if the value of the field is `CYCLE512`"] + #[inline(always)] + pub fn is_cycle512(&self) -> bool { + **self == STARTUP_A::CYCLE512 + } + #[doc = "Checks if the value of the field is `CYCLE1024`"] + #[inline(always)] + pub fn is_cycle1024(&self) -> bool { + **self == STARTUP_A::CYCLE1024 + } + #[doc = "Checks if the value of the field is `CYCLE2048`"] + #[inline(always)] + pub fn is_cycle2048(&self) -> bool { + **self == STARTUP_A::CYCLE2048 + } + #[doc = "Checks if the value of the field is `CYCLE4096`"] + #[inline(always)] + pub fn is_cycle4096(&self) -> bool { + **self == STARTUP_A::CYCLE4096 + } + #[doc = "Checks if the value of the field is `CYCLE8192`"] + #[inline(always)] + pub fn is_cycle8192(&self) -> bool { + **self == STARTUP_A::CYCLE8192 + } + #[doc = "Checks if the value of the field is `CYCLE16384`"] + #[inline(always)] + pub fn is_cycle16384(&self) -> bool { + **self == STARTUP_A::CYCLE16384 + } + #[doc = "Checks if the value of the field is `CYCLE32768`"] + #[inline(always)] + pub fn is_cycle32768(&self) -> bool { + **self == STARTUP_A::CYCLE32768 + } +} +impl core::ops::Deref for STARTUP_R { + type Target = crate::FieldReader<u8, STARTUP_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub struct STARTUP_W<'a> { + w: &'a mut W, +} +impl<'a> STARTUP_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: STARTUP_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "31 us"] + #[inline(always)] + pub fn cycle1(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1) + } + #[doc = "61 us"] + #[inline(always)] + pub fn cycle2(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2) + } + #[doc = "122 us"] + #[inline(always)] + pub fn cycle4(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4) + } + #[doc = "244 us"] + #[inline(always)] + pub fn cycle8(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8) + } + #[doc = "488 us"] + #[inline(always)] + pub fn cycle16(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16) + } + #[doc = "977 us"] + #[inline(always)] + pub fn cycle32(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32) + } + #[doc = "1953 us"] + #[inline(always)] + pub fn cycle64(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE64) + } + #[doc = "3906 us"] + #[inline(always)] + pub fn cycle128(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE128) + } + #[doc = "7813 us"] + #[inline(always)] + pub fn cycle256(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE256) + } + #[doc = "15625 us"] + #[inline(always)] + pub fn cycle512(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE512) + } + #[doc = "31250 us"] + #[inline(always)] + pub fn cycle1024(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE1024) + } + #[doc = "62500 us"] + #[inline(always)] + pub fn cycle2048(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE2048) + } + #[doc = "125000 us"] + #[inline(always)] + pub fn cycle4096(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE4096) + } + #[doc = "250000 us"] + #[inline(always)] + pub fn cycle8192(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE8192) + } + #[doc = "500000 us"] + #[inline(always)] + pub fn cycle16384(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE16384) + } + #[doc = "1000000 us"] + #[inline(always)] + pub fn cycle32768(self) -> &'a mut W { + self.variant(STARTUP_A::CYCLE32768) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u16 & 0x0f) << 12); + self.w + } +} +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 0x07) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&mut self) -> XTALEN_W { + XTALEN_W { w: self } + } + #[doc = "Bit 3 - Xosc Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&mut self) -> CFDEN_W { + CFDEN_W { w: self } + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&mut self) -> SWBEN_W { + SWBEN_W { w: self } + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&mut self) -> ONDEMAND_W { + ONDEMAND_W { w: self } + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&mut self) -> GAIN_W { + GAIN_W { w: self } + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&mut self) -> AMPGC_W { + AMPGC_W { w: self } + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&mut self) -> STARTUP_W { + STARTUP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x80 + } +} |