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-rw-r--r--src/port/group/ctrl.rs102
-rw-r--r--src/port/group/dir.rs64
-rw-r--r--src/port/group/dirclr.rs64
-rw-r--r--src/port/group/dirset.rs64
-rw-r--r--src/port/group/dirtgl.rs64
-rw-r--r--src/port/group/evctrl.rs613
-rw-r--r--src/port/group/in_.rs31
-rw-r--r--src/port/group/out.rs64
-rw-r--r--src/port/group/outclr.rs64
-rw-r--r--src/port/group/outset.rs64
-rw-r--r--src/port/group/outtgl.rs64
-rw-r--r--src/port/group/pincfg.rs251
-rw-r--r--src/port/group/pmux.rs139
-rw-r--r--src/port/group/wrconfig.rs268
14 files changed, 1916 insertions, 0 deletions
diff --git a/src/port/group/ctrl.rs b/src/port/group/ctrl.rs
new file mode 100644
index 0000000..e9870cd
--- /dev/null
+++ b/src/port/group/ctrl.rs
@@ -0,0 +1,102 @@
+#[doc = "Register `CTRL` reader"]
+pub struct R(crate::R<CTRL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<CTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<CTRL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<CTRL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `CTRL` writer"]
+pub struct W(crate::W<CTRL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<CTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<CTRL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<CTRL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `SAMPLING` reader - Input Sampling Mode"]
+pub struct SAMPLING_R(crate::FieldReader<u32, u32>);
+impl SAMPLING_R {
+ pub(crate) fn new(bits: u32) -> Self {
+ SAMPLING_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for SAMPLING_R {
+ type Target = crate::FieldReader<u32, u32>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `SAMPLING` writer - Input Sampling Mode"]
+pub struct SAMPLING_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SAMPLING_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u32) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0xffff_ffff) | (value as u32 & 0xffff_ffff);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bits 0:31 - Input Sampling Mode"]
+ #[inline(always)]
+ pub fn sampling(&self) -> SAMPLING_R {
+ SAMPLING_R::new((self.bits & 0xffff_ffff) as u32)
+ }
+}
+impl W {
+ #[doc = "Bits 0:31 - Input Sampling Mode"]
+ #[inline(always)]
+ pub fn sampling(&mut self) -> SAMPLING_W {
+ SAMPLING_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CTRL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/dir.rs b/src/port/group/dir.rs
new file mode 100644
index 0000000..e04452f
--- /dev/null
+++ b/src/port/group/dir.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `DIR` reader"]
+pub struct R(crate::R<DIR_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<DIR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<DIR_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<DIR_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `DIR` writer"]
+pub struct W(crate::W<DIR_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<DIR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<DIR_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<DIR_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"]
+pub struct DIR_SPEC;
+impl crate::RegisterSpec for DIR_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [dir::R](R) reader structure"]
+impl crate::Readable for DIR_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"]
+impl crate::Writable for DIR_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets DIR to value 0"]
+impl crate::Resettable for DIR_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/dirclr.rs b/src/port/group/dirclr.rs
new file mode 100644
index 0000000..5e6d73d
--- /dev/null
+++ b/src/port/group/dirclr.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `DIRCLR` reader"]
+pub struct R(crate::R<DIRCLR_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<DIRCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<DIRCLR_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<DIRCLR_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `DIRCLR` writer"]
+pub struct W(crate::W<DIRCLR_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<DIRCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<DIRCLR_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<DIRCLR_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"]
+pub struct DIRCLR_SPEC;
+impl crate::RegisterSpec for DIRCLR_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [dirclr::R](R) reader structure"]
+impl crate::Readable for DIRCLR_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"]
+impl crate::Writable for DIRCLR_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets DIRCLR to value 0"]
+impl crate::Resettable for DIRCLR_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/dirset.rs b/src/port/group/dirset.rs
new file mode 100644
index 0000000..eaa86e1
--- /dev/null
+++ b/src/port/group/dirset.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `DIRSET` reader"]
+pub struct R(crate::R<DIRSET_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<DIRSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<DIRSET_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<DIRSET_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `DIRSET` writer"]
+pub struct W(crate::W<DIRSET_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<DIRSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<DIRSET_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<DIRSET_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"]
+pub struct DIRSET_SPEC;
+impl crate::RegisterSpec for DIRSET_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [dirset::R](R) reader structure"]
+impl crate::Readable for DIRSET_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"]
+impl crate::Writable for DIRSET_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets DIRSET to value 0"]
+impl crate::Resettable for DIRSET_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/dirtgl.rs b/src/port/group/dirtgl.rs
new file mode 100644
index 0000000..fbd0214
--- /dev/null
+++ b/src/port/group/dirtgl.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `DIRTGL` reader"]
+pub struct R(crate::R<DIRTGL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<DIRTGL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<DIRTGL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<DIRTGL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `DIRTGL` writer"]
+pub struct W(crate::W<DIRTGL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<DIRTGL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<DIRTGL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<DIRTGL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"]
+pub struct DIRTGL_SPEC;
+impl crate::RegisterSpec for DIRTGL_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [dirtgl::R](R) reader structure"]
+impl crate::Readable for DIRTGL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"]
+impl crate::Writable for DIRTGL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets DIRTGL to value 0"]
+impl crate::Resettable for DIRTGL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/evctrl.rs b/src/port/group/evctrl.rs
new file mode 100644
index 0000000..efbc564
--- /dev/null
+++ b/src/port/group/evctrl.rs
@@ -0,0 +1,613 @@
+#[doc = "Register `EVCTRL` reader"]
+pub struct R(crate::R<EVCTRL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<EVCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<EVCTRL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<EVCTRL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `EVCTRL` writer"]
+pub struct W(crate::W<EVCTRL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<EVCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<EVCTRL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<EVCTRL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"]
+pub struct PID0_R(crate::FieldReader<u8, u8>);
+impl PID0_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PID0_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PID0_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"]
+pub struct PID0_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PID0_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x1f) | (value as u32 & 0x1f);
+ self.w
+ }
+}
+#[doc = "Port Event Action 0\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum EVACT0_A {
+ #[doc = "0: Event output to pin"]
+ OUT = 0,
+ #[doc = "1: Set output register of pin on event"]
+ SET = 1,
+ #[doc = "2: Clear output register of pin on event"]
+ CLR = 2,
+ #[doc = "3: Toggle output register of pin on event"]
+ TGL = 3,
+}
+impl From<EVACT0_A> for u8 {
+ #[inline(always)]
+ fn from(variant: EVACT0_A) -> Self {
+ variant as _
+ }
+}
+#[doc = "Field `EVACT0` reader - Port Event Action 0"]
+pub struct EVACT0_R(crate::FieldReader<u8, EVACT0_A>);
+impl EVACT0_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ EVACT0_R(crate::FieldReader::new(bits))
+ }
+ #[doc = r"Get enumerated values variant"]
+ #[inline(always)]
+ pub fn variant(&self) -> EVACT0_A {
+ match self.bits {
+ 0 => EVACT0_A::OUT,
+ 1 => EVACT0_A::SET,
+ 2 => EVACT0_A::CLR,
+ 3 => EVACT0_A::TGL,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Checks if the value of the field is `OUT`"]
+ #[inline(always)]
+ pub fn is_out(&self) -> bool {
+ **self == EVACT0_A::OUT
+ }
+ #[doc = "Checks if the value of the field is `SET`"]
+ #[inline(always)]
+ pub fn is_set(&self) -> bool {
+ **self == EVACT0_A::SET
+ }
+ #[doc = "Checks if the value of the field is `CLR`"]
+ #[inline(always)]
+ pub fn is_clr(&self) -> bool {
+ **self == EVACT0_A::CLR
+ }
+ #[doc = "Checks if the value of the field is `TGL`"]
+ #[inline(always)]
+ pub fn is_tgl(&self) -> bool {
+ **self == EVACT0_A::TGL
+ }
+}
+impl core::ops::Deref for EVACT0_R {
+ type Target = crate::FieldReader<u8, EVACT0_A>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EVACT0` writer - Port Event Action 0"]
+pub struct EVACT0_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EVACT0_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: EVACT0_A) -> &'a mut W {
+ self.bits(variant.into())
+ }
+ #[doc = "Event output to pin"]
+ #[inline(always)]
+ pub fn out(self) -> &'a mut W {
+ self.variant(EVACT0_A::OUT)
+ }
+ #[doc = "Set output register of pin on event"]
+ #[inline(always)]
+ pub fn set(self) -> &'a mut W {
+ self.variant(EVACT0_A::SET)
+ }
+ #[doc = "Clear output register of pin on event"]
+ #[inline(always)]
+ pub fn clr(self) -> &'a mut W {
+ self.variant(EVACT0_A::CLR)
+ }
+ #[doc = "Toggle output register of pin on event"]
+ #[inline(always)]
+ pub fn tgl(self) -> &'a mut W {
+ self.variant(EVACT0_A::TGL)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x03 << 5)) | ((value as u32 & 0x03) << 5);
+ self.w
+ }
+}
+#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"]
+pub struct PORTEI0_R(crate::FieldReader<bool, bool>);
+impl PORTEI0_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PORTEI0_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PORTEI0_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"]
+pub struct PORTEI0_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PORTEI0_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+ self.w
+ }
+}
+#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"]
+pub struct PID1_R(crate::FieldReader<u8, u8>);
+impl PID1_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PID1_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PID1_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"]
+pub struct PID1_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PID1_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8);
+ self.w
+ }
+}
+#[doc = "Field `EVACT1` reader - Port Event Action 1"]
+pub struct EVACT1_R(crate::FieldReader<u8, u8>);
+impl EVACT1_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ EVACT1_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EVACT1_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EVACT1` writer - Port Event Action 1"]
+pub struct EVACT1_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EVACT1_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x03 << 13)) | ((value as u32 & 0x03) << 13);
+ self.w
+ }
+}
+#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"]
+pub struct PORTEI1_R(crate::FieldReader<bool, bool>);
+impl PORTEI1_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PORTEI1_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PORTEI1_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"]
+pub struct PORTEI1_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PORTEI1_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+ self.w
+ }
+}
+#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"]
+pub struct PID2_R(crate::FieldReader<u8, u8>);
+impl PID2_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PID2_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PID2_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"]
+pub struct PID2_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PID2_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x1f << 16)) | ((value as u32 & 0x1f) << 16);
+ self.w
+ }
+}
+#[doc = "Field `EVACT2` reader - Port Event Action 2"]
+pub struct EVACT2_R(crate::FieldReader<u8, u8>);
+impl EVACT2_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ EVACT2_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EVACT2_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EVACT2` writer - Port Event Action 2"]
+pub struct EVACT2_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EVACT2_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x03 << 21)) | ((value as u32 & 0x03) << 21);
+ self.w
+ }
+}
+#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"]
+pub struct PORTEI2_R(crate::FieldReader<bool, bool>);
+impl PORTEI2_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PORTEI2_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PORTEI2_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"]
+pub struct PORTEI2_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PORTEI2_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
+ self.w
+ }
+}
+#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"]
+pub struct PID3_R(crate::FieldReader<u8, u8>);
+impl PID3_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PID3_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PID3_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"]
+pub struct PID3_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PID3_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x1f << 24)) | ((value as u32 & 0x1f) << 24);
+ self.w
+ }
+}
+#[doc = "Field `EVACT3` reader - Port Event Action 3"]
+pub struct EVACT3_R(crate::FieldReader<u8, u8>);
+impl EVACT3_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ EVACT3_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EVACT3_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EVACT3` writer - Port Event Action 3"]
+pub struct EVACT3_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EVACT3_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x03 << 29)) | ((value as u32 & 0x03) << 29);
+ self.w
+ }
+}
+#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"]
+pub struct PORTEI3_R(crate::FieldReader<bool, bool>);
+impl PORTEI3_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PORTEI3_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PORTEI3_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"]
+pub struct PORTEI3_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PORTEI3_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bits 0:4 - Port Event Pin Identifier 0"]
+ #[inline(always)]
+ pub fn pid0(&self) -> PID0_R {
+ PID0_R::new((self.bits & 0x1f) as u8)
+ }
+ #[doc = "Bits 5:6 - Port Event Action 0"]
+ #[inline(always)]
+ pub fn evact0(&self) -> EVACT0_R {
+ EVACT0_R::new(((self.bits >> 5) & 0x03) as u8)
+ }
+ #[doc = "Bit 7 - Port Event Enable Input 0"]
+ #[inline(always)]
+ pub fn portei0(&self) -> PORTEI0_R {
+ PORTEI0_R::new(((self.bits >> 7) & 0x01) != 0)
+ }
+ #[doc = "Bits 8:12 - Port Event Pin Identifier 1"]
+ #[inline(always)]
+ pub fn pid1(&self) -> PID1_R {
+ PID1_R::new(((self.bits >> 8) & 0x1f) as u8)
+ }
+ #[doc = "Bits 13:14 - Port Event Action 1"]
+ #[inline(always)]
+ pub fn evact1(&self) -> EVACT1_R {
+ EVACT1_R::new(((self.bits >> 13) & 0x03) as u8)
+ }
+ #[doc = "Bit 15 - Port Event Enable Input 1"]
+ #[inline(always)]
+ pub fn portei1(&self) -> PORTEI1_R {
+ PORTEI1_R::new(((self.bits >> 15) & 0x01) != 0)
+ }
+ #[doc = "Bits 16:20 - Port Event Pin Identifier 2"]
+ #[inline(always)]
+ pub fn pid2(&self) -> PID2_R {
+ PID2_R::new(((self.bits >> 16) & 0x1f) as u8)
+ }
+ #[doc = "Bits 21:22 - Port Event Action 2"]
+ #[inline(always)]
+ pub fn evact2(&self) -> EVACT2_R {
+ EVACT2_R::new(((self.bits >> 21) & 0x03) as u8)
+ }
+ #[doc = "Bit 23 - Port Event Enable Input 2"]
+ #[inline(always)]
+ pub fn portei2(&self) -> PORTEI2_R {
+ PORTEI2_R::new(((self.bits >> 23) & 0x01) != 0)
+ }
+ #[doc = "Bits 24:28 - Port Event Pin Identifier 3"]
+ #[inline(always)]
+ pub fn pid3(&self) -> PID3_R {
+ PID3_R::new(((self.bits >> 24) & 0x1f) as u8)
+ }
+ #[doc = "Bits 29:30 - Port Event Action 3"]
+ #[inline(always)]
+ pub fn evact3(&self) -> EVACT3_R {
+ EVACT3_R::new(((self.bits >> 29) & 0x03) as u8)
+ }
+ #[doc = "Bit 31 - Port Event Enable Input 3"]
+ #[inline(always)]
+ pub fn portei3(&self) -> PORTEI3_R {
+ PORTEI3_R::new(((self.bits >> 31) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 0:4 - Port Event Pin Identifier 0"]
+ #[inline(always)]
+ pub fn pid0(&mut self) -> PID0_W {
+ PID0_W { w: self }
+ }
+ #[doc = "Bits 5:6 - Port Event Action 0"]
+ #[inline(always)]
+ pub fn evact0(&mut self) -> EVACT0_W {
+ EVACT0_W { w: self }
+ }
+ #[doc = "Bit 7 - Port Event Enable Input 0"]
+ #[inline(always)]
+ pub fn portei0(&mut self) -> PORTEI0_W {
+ PORTEI0_W { w: self }
+ }
+ #[doc = "Bits 8:12 - Port Event Pin Identifier 1"]
+ #[inline(always)]
+ pub fn pid1(&mut self) -> PID1_W {
+ PID1_W { w: self }
+ }
+ #[doc = "Bits 13:14 - Port Event Action 1"]
+ #[inline(always)]
+ pub fn evact1(&mut self) -> EVACT1_W {
+ EVACT1_W { w: self }
+ }
+ #[doc = "Bit 15 - Port Event Enable Input 1"]
+ #[inline(always)]
+ pub fn portei1(&mut self) -> PORTEI1_W {
+ PORTEI1_W { w: self }
+ }
+ #[doc = "Bits 16:20 - Port Event Pin Identifier 2"]
+ #[inline(always)]
+ pub fn pid2(&mut self) -> PID2_W {
+ PID2_W { w: self }
+ }
+ #[doc = "Bits 21:22 - Port Event Action 2"]
+ #[inline(always)]
+ pub fn evact2(&mut self) -> EVACT2_W {
+ EVACT2_W { w: self }
+ }
+ #[doc = "Bit 23 - Port Event Enable Input 2"]
+ #[inline(always)]
+ pub fn portei2(&mut self) -> PORTEI2_W {
+ PORTEI2_W { w: self }
+ }
+ #[doc = "Bits 24:28 - Port Event Pin Identifier 3"]
+ #[inline(always)]
+ pub fn pid3(&mut self) -> PID3_W {
+ PID3_W { w: self }
+ }
+ #[doc = "Bits 29:30 - Port Event Action 3"]
+ #[inline(always)]
+ pub fn evact3(&mut self) -> EVACT3_W {
+ EVACT3_W { w: self }
+ }
+ #[doc = "Bit 31 - Port Event Enable Input 3"]
+ #[inline(always)]
+ pub fn portei3(&mut self) -> PORTEI3_W {
+ PORTEI3_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"]
+pub struct EVCTRL_SPEC;
+impl crate::RegisterSpec for EVCTRL_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [evctrl::R](R) reader structure"]
+impl crate::Readable for EVCTRL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"]
+impl crate::Writable for EVCTRL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets EVCTRL to value 0"]
+impl crate::Resettable for EVCTRL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/in_.rs b/src/port/group/in_.rs
new file mode 100644
index 0000000..1c8e739
--- /dev/null
+++ b/src/port/group/in_.rs
@@ -0,0 +1,31 @@
+#[doc = "Register `IN` reader"]
+pub struct R(crate::R<IN_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<IN_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<IN_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<IN_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"]
+pub struct IN_SPEC;
+impl crate::RegisterSpec for IN_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [in_::R](R) reader structure"]
+impl crate::Readable for IN_SPEC {
+ type Reader = R;
+}
+#[doc = "`reset()` method sets IN to value 0"]
+impl crate::Resettable for IN_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/out.rs b/src/port/group/out.rs
new file mode 100644
index 0000000..092e8db
--- /dev/null
+++ b/src/port/group/out.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `OUT` reader"]
+pub struct R(crate::R<OUT_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OUT_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OUT_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OUT_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OUT` writer"]
+pub struct W(crate::W<OUT_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OUT_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OUT_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OUT_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"]
+pub struct OUT_SPEC;
+impl crate::RegisterSpec for OUT_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [out::R](R) reader structure"]
+impl crate::Readable for OUT_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"]
+impl crate::Writable for OUT_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OUT to value 0"]
+impl crate::Resettable for OUT_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/outclr.rs b/src/port/group/outclr.rs
new file mode 100644
index 0000000..6e73439
--- /dev/null
+++ b/src/port/group/outclr.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `OUTCLR` reader"]
+pub struct R(crate::R<OUTCLR_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OUTCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OUTCLR_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OUTCLR_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OUTCLR` writer"]
+pub struct W(crate::W<OUTCLR_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OUTCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OUTCLR_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OUTCLR_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"]
+pub struct OUTCLR_SPEC;
+impl crate::RegisterSpec for OUTCLR_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [outclr::R](R) reader structure"]
+impl crate::Readable for OUTCLR_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"]
+impl crate::Writable for OUTCLR_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OUTCLR to value 0"]
+impl crate::Resettable for OUTCLR_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/outset.rs b/src/port/group/outset.rs
new file mode 100644
index 0000000..6d39122
--- /dev/null
+++ b/src/port/group/outset.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `OUTSET` reader"]
+pub struct R(crate::R<OUTSET_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OUTSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OUTSET_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OUTSET_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OUTSET` writer"]
+pub struct W(crate::W<OUTSET_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OUTSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OUTSET_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OUTSET_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"]
+pub struct OUTSET_SPEC;
+impl crate::RegisterSpec for OUTSET_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [outset::R](R) reader structure"]
+impl crate::Readable for OUTSET_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"]
+impl crate::Writable for OUTSET_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OUTSET to value 0"]
+impl crate::Resettable for OUTSET_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/outtgl.rs b/src/port/group/outtgl.rs
new file mode 100644
index 0000000..0f3d87d
--- /dev/null
+++ b/src/port/group/outtgl.rs
@@ -0,0 +1,64 @@
+#[doc = "Register `OUTTGL` reader"]
+pub struct R(crate::R<OUTTGL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OUTTGL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OUTTGL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OUTTGL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OUTTGL` writer"]
+pub struct W(crate::W<OUTTGL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OUTTGL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OUTTGL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OUTTGL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+impl W {
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"]
+pub struct OUTTGL_SPEC;
+impl crate::RegisterSpec for OUTTGL_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [outtgl::R](R) reader structure"]
+impl crate::Readable for OUTTGL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"]
+impl crate::Writable for OUTTGL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OUTTGL to value 0"]
+impl crate::Resettable for OUTTGL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/pincfg.rs b/src/port/group/pincfg.rs
new file mode 100644
index 0000000..1427762
--- /dev/null
+++ b/src/port/group/pincfg.rs
@@ -0,0 +1,251 @@
+#[doc = "Register `PINCFG[%s]` reader"]
+pub struct R(crate::R<PINCFG_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<PINCFG_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<PINCFG_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<PINCFG_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `PINCFG[%s]` writer"]
+pub struct W(crate::W<PINCFG_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<PINCFG_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<PINCFG_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<PINCFG_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"]
+pub struct PMUXEN_R(crate::FieldReader<bool, bool>);
+impl PMUXEN_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PMUXEN_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PMUXEN_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"]
+pub struct PMUXEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PMUXEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `INEN` reader - Input Enable"]
+pub struct INEN_R(crate::FieldReader<bool, bool>);
+impl INEN_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ INEN_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for INEN_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `INEN` writer - Input Enable"]
+pub struct INEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> INEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `PULLEN` reader - Pull Enable"]
+pub struct PULLEN_R(crate::FieldReader<bool, bool>);
+impl PULLEN_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PULLEN_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PULLEN_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PULLEN` writer - Pull Enable"]
+pub struct PULLEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PULLEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
+ self.w
+ }
+}
+#[doc = "Field `DRVSTR` reader - Output Driver Strength Selection"]
+pub struct DRVSTR_R(crate::FieldReader<bool, bool>);
+impl DRVSTR_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ DRVSTR_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for DRVSTR_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"]
+pub struct DRVSTR_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> DRVSTR_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u8 & 0x01) << 6);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - Select Peripheral Multiplexer"]
+ #[inline(always)]
+ pub fn pmuxen(&self) -> PMUXEN_R {
+ PMUXEN_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - Input Enable"]
+ #[inline(always)]
+ pub fn inen(&self) -> INEN_R {
+ INEN_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - Pull Enable"]
+ #[inline(always)]
+ pub fn pullen(&self) -> PULLEN_R {
+ PULLEN_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+ #[doc = "Bit 6 - Output Driver Strength Selection"]
+ #[inline(always)]
+ pub fn drvstr(&self) -> DRVSTR_R {
+ DRVSTR_R::new(((self.bits >> 6) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Select Peripheral Multiplexer"]
+ #[inline(always)]
+ pub fn pmuxen(&mut self) -> PMUXEN_W {
+ PMUXEN_W { w: self }
+ }
+ #[doc = "Bit 1 - Input Enable"]
+ #[inline(always)]
+ pub fn inen(&mut self) -> INEN_W {
+ INEN_W { w: self }
+ }
+ #[doc = "Bit 2 - Pull Enable"]
+ #[inline(always)]
+ pub fn pullen(&mut self) -> PULLEN_W {
+ PULLEN_W { w: self }
+ }
+ #[doc = "Bit 6 - Output Driver Strength Selection"]
+ #[inline(always)]
+ pub fn drvstr(&mut self) -> DRVSTR_W {
+ DRVSTR_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Pin Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg](index.html) module"]
+pub struct PINCFG_SPEC;
+impl crate::RegisterSpec for PINCFG_SPEC {
+ type Ux = u8;
+}
+#[doc = "`read()` method returns [pincfg::R](R) reader structure"]
+impl crate::Readable for PINCFG_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pincfg::W](W) writer structure"]
+impl crate::Writable for PINCFG_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets PINCFG[%s]
+to value 0"]
+impl crate::Resettable for PINCFG_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/pmux.rs b/src/port/group/pmux.rs
new file mode 100644
index 0000000..4286b2b
--- /dev/null
+++ b/src/port/group/pmux.rs
@@ -0,0 +1,139 @@
+#[doc = "Register `PMUX[%s]` reader"]
+pub struct R(crate::R<PMUX_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<PMUX_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<PMUX_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<PMUX_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `PMUX[%s]` writer"]
+pub struct W(crate::W<PMUX_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<PMUX_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<PMUX_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<PMUX_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"]
+pub struct PMUXE_R(crate::FieldReader<u8, u8>);
+impl PMUXE_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PMUXE_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PMUXE_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"]
+pub struct PMUXE_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PMUXE_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x0f) | (value as u8 & 0x0f);
+ self.w
+ }
+}
+#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"]
+pub struct PMUXO_R(crate::FieldReader<u8, u8>);
+impl PMUXO_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ PMUXO_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PMUXO_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"]
+pub struct PMUXO_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PMUXO_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u8 & 0x0f) << 4);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"]
+ #[inline(always)]
+ pub fn pmuxe(&self) -> PMUXE_R {
+ PMUXE_R::new((self.bits & 0x0f) as u8)
+ }
+ #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"]
+ #[inline(always)]
+ pub fn pmuxo(&self) -> PMUXO_R {
+ PMUXO_R::new(((self.bits >> 4) & 0x0f) as u8)
+ }
+}
+impl W {
+ #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"]
+ #[inline(always)]
+ pub fn pmuxe(&mut self) -> PMUXE_W {
+ PMUXE_W { w: self }
+ }
+ #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"]
+ #[inline(always)]
+ pub fn pmuxo(&mut self) -> PMUXO_W {
+ PMUXO_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Peripheral Multiplexing n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux](index.html) module"]
+pub struct PMUX_SPEC;
+impl crate::RegisterSpec for PMUX_SPEC {
+ type Ux = u8;
+}
+#[doc = "`read()` method returns [pmux::R](R) reader structure"]
+impl crate::Readable for PMUX_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pmux::W](W) writer structure"]
+impl crate::Writable for PMUX_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets PMUX[%s]
+to value 0"]
+impl crate::Resettable for PMUX_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/port/group/wrconfig.rs b/src/port/group/wrconfig.rs
new file mode 100644
index 0000000..c87e4f1
--- /dev/null
+++ b/src/port/group/wrconfig.rs
@@ -0,0 +1,268 @@
+#[doc = "Register `WRCONFIG` writer"]
+pub struct W(crate::W<WRCONFIG_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<WRCONFIG_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<WRCONFIG_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<WRCONFIG_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"]
+pub struct PINMASK_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PINMASK_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u16) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
+ self.w
+ }
+}
+#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"]
+pub struct PMUXEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PMUXEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+ self.w
+ }
+}
+#[doc = "Field `INEN` writer - Input Enable"]
+pub struct INEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> INEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+ self.w
+ }
+}
+#[doc = "Field `PULLEN` writer - Pull Enable"]
+pub struct PULLEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PULLEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
+ self.w
+ }
+}
+#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"]
+pub struct DRVSTR_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> DRVSTR_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
+ self.w
+ }
+}
+#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"]
+pub struct PMUX_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PMUX_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x0f << 24)) | ((value as u32 & 0x0f) << 24);
+ self.w
+ }
+}
+#[doc = "Field `WRPMUX` writer - Write PMUX Registers"]
+pub struct WRPMUX_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> WRPMUX_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
+ self.w
+ }
+}
+#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"]
+pub struct WRPINCFG_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> WRPINCFG_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
+ self.w
+ }
+}
+#[doc = "Field `HWSEL` writer - Half-Word Select"]
+pub struct HWSEL_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> HWSEL_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
+ self.w
+ }
+}
+impl W {
+ #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"]
+ #[inline(always)]
+ pub fn pinmask(&mut self) -> PINMASK_W {
+ PINMASK_W { w: self }
+ }
+ #[doc = "Bit 16 - Select Peripheral Multiplexer"]
+ #[inline(always)]
+ pub fn pmuxen(&mut self) -> PMUXEN_W {
+ PMUXEN_W { w: self }
+ }
+ #[doc = "Bit 17 - Input Enable"]
+ #[inline(always)]
+ pub fn inen(&mut self) -> INEN_W {
+ INEN_W { w: self }
+ }
+ #[doc = "Bit 18 - Pull Enable"]
+ #[inline(always)]
+ pub fn pullen(&mut self) -> PULLEN_W {
+ PULLEN_W { w: self }
+ }
+ #[doc = "Bit 22 - Output Driver Strength Selection"]
+ #[inline(always)]
+ pub fn drvstr(&mut self) -> DRVSTR_W {
+ DRVSTR_W { w: self }
+ }
+ #[doc = "Bits 24:27 - Peripheral Multiplexing Template"]
+ #[inline(always)]
+ pub fn pmux(&mut self) -> PMUX_W {
+ PMUX_W { w: self }
+ }
+ #[doc = "Bit 28 - Write PMUX Registers"]
+ #[inline(always)]
+ pub fn wrpmux(&mut self) -> WRPMUX_W {
+ WRPMUX_W { w: self }
+ }
+ #[doc = "Bit 30 - Write PINCFG Registers"]
+ #[inline(always)]
+ pub fn wrpincfg(&mut self) -> WRPINCFG_W {
+ WRPINCFG_W { w: self }
+ }
+ #[doc = "Bit 31 - Half-Word Select"]
+ #[inline(always)]
+ pub fn hwsel(&mut self) -> HWSEL_W {
+ HWSEL_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"]
+pub struct WRCONFIG_SPEC;
+impl crate::RegisterSpec for WRCONFIG_SPEC {
+ type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"]
+impl crate::Writable for WRCONFIG_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets WRCONFIG to value 0"]
+impl crate::Resettable for WRCONFIG_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
generated by cgit v1.2.3-70-g09d2 (git 2.51.1) at 2025-12-06 06:49:44 +0000