diff options
Diffstat (limited to 'src/sercom0/i2cm')
| -rw-r--r-- | src/sercom0/i2cm/addr.rs | 276 | ||||
| -rw-r--r-- | src/sercom0/i2cm/baud.rs | 210 | ||||
| -rw-r--r-- | src/sercom0/i2cm/ctrla.rs | 891 | ||||
| -rw-r--r-- | src/sercom0/i2cm/ctrlb.rs | 240 | ||||
| -rw-r--r-- | src/sercom0/i2cm/data.rs | 102 | ||||
| -rw-r--r-- | src/sercom0/i2cm/dbgctrl.rs | 112 | ||||
| -rw-r--r-- | src/sercom0/i2cm/intenclr.rs | 204 | ||||
| -rw-r--r-- | src/sercom0/i2cm/intenset.rs | 204 | ||||
| -rw-r--r-- | src/sercom0/i2cm/intflag.rs | 204 | ||||
| -rw-r--r-- | src/sercom0/i2cm/status.rs | 470 | ||||
| -rw-r--r-- | src/sercom0/i2cm/syncbusy.rs | 90 |
11 files changed, 3003 insertions, 0 deletions
diff --git a/src/sercom0/i2cm/addr.rs b/src/sercom0/i2cm/addr.rs new file mode 100644 index 0000000..26dce82 --- /dev/null +++ b/src/sercom0/i2cm/addr.rs @@ -0,0 +1,276 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R<ADDR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<ADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<ADDR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<ADDR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W<ADDR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<ADDR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<ADDR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<ADDR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub struct ADDR_R(crate::FieldReader<u16, u16>); +impl ADDR_R { + pub(crate) fn new(bits: u16) -> Self { + ADDR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADDR_R { + type Target = crate::FieldReader<u16, u16>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADDR` writer - Address Value"] +pub struct ADDR_W<'a> { + w: &'a mut W, +} +impl<'a> ADDR_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u16) -> &'a mut W { + self.w.bits = (self.w.bits & !0x07ff) | (value as u32 & 0x07ff); + self.w + } +} +#[doc = "Field `LENEN` reader - Length Enable"] +pub struct LENEN_R(crate::FieldReader<bool, bool>); +impl LENEN_R { + pub(crate) fn new(bits: bool) -> Self { + LENEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENEN` writer - Length Enable"] +pub struct LENEN_W<'a> { + w: &'a mut W, +} +impl<'a> LENEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `HS` reader - High Speed Mode"] +pub struct HS_R(crate::FieldReader<bool, bool>); +impl HS_R { + pub(crate) fn new(bits: bool) -> Self { + HS_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HS_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HS` writer - High Speed Mode"] +pub struct HS_W<'a> { + w: &'a mut W, +} +impl<'a> HS_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub struct TENBITEN_R(crate::FieldReader<bool, bool>); +impl TENBITEN_R { + pub(crate) fn new(bits: bool) -> Self { + TENBITEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TENBITEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub struct TENBITEN_W<'a> { + w: &'a mut W, +} +impl<'a> TENBITEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `LEN` reader - Length"] +pub struct LEN_R(crate::FieldReader<u8, u8>); +impl LEN_R { + pub(crate) fn new(bits: u8) -> Self { + LEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LEN_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LEN` writer - Length"] +pub struct LEN_W<'a> { + w: &'a mut W, +} +impl<'a> LEN_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W { w: self } + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&mut self) -> LENEN_W { + LENEN_W { w: self } + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&mut self) -> HS_W { + HS_W { w: self } + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&mut self) -> TENBITEN_W { + TENBITEN_W { w: self } + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&mut self) -> LEN_W { + LEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/baud.rs b/src/sercom0/i2cm/baud.rs new file mode 100644 index 0000000..0866b75 --- /dev/null +++ b/src/sercom0/i2cm/baud.rs @@ -0,0 +1,210 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R<BAUD_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<BAUD_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<BAUD_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<BAUD_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W<BAUD_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<BAUD_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<BAUD_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<BAUD_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub struct BAUD_R(crate::FieldReader<u8, u8>); +impl BAUD_R { + pub(crate) fn new(bits: u8) -> Self { + BAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUD_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub struct BAUD_W<'a> { + w: &'a mut W, +} +impl<'a> BAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff); + self.w + } +} +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub struct BAUDLOW_R(crate::FieldReader<u8, u8>); +impl BAUDLOW_R { + pub(crate) fn new(bits: u8) -> Self { + BAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BAUDLOW_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub struct BAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> BAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8); + self.w + } +} +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub struct HSBAUD_R(crate::FieldReader<u8, u8>); +impl HSBAUD_R { + pub(crate) fn new(bits: u8) -> Self { + HSBAUD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUD_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub struct HSBAUD_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 16)) | ((value as u32 & 0xff) << 16); + self.w + } +} +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_R(crate::FieldReader<u8, u8>); +impl HSBAUDLOW_R { + pub(crate) fn new(bits: u8) -> Self { + HSBAUDLOW_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSBAUDLOW_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub struct HSBAUDLOW_W<'a> { + w: &'a mut W, +} +impl<'a> HSBAUDLOW_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0xff << 24)) | ((value as u32 & 0xff) << 24); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&mut self) -> BAUD_W { + BAUD_W { w: self } + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&mut self) -> BAUDLOW_W { + BAUDLOW_W { w: self } + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&mut self) -> HSBAUD_W { + HSBAUD_W { w: self } + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W { + HSBAUDLOW_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/ctrla.rs b/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 0000000..6aa87b5 --- /dev/null +++ b/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,891 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R<CTRLA_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CTRLA_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CTRLA_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W<CTRLA_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CTRLA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CTRLA_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CTRLA_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub struct SWRST_R(crate::FieldReader<bool, bool>); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub struct SWRST_W<'a> { + w: &'a mut W, +} +impl<'a> SWRST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` writer - Enable"] +pub struct ENABLE_W<'a> { + w: &'a mut W, +} +impl<'a> ENABLE_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: USART with external clock"] + USART_EXT_CLK = 0, + #[doc = "1: USART with internal clock"] + USART_INT_CLK = 1, + #[doc = "2: SPI in slave operation"] + SPI_SLAVE = 2, + #[doc = "3: SPI in master operation"] + SPI_MASTER = 3, + #[doc = "4: I2C slave operation"] + I2C_SLAVE = 4, + #[doc = "5: I2C master operation"] + I2C_MASTER = 5, +} +impl From<MODE_A> for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +#[doc = "Field `MODE` reader - Operating Mode"] +pub struct MODE_R(crate::FieldReader<u8, MODE_A>); +impl MODE_R { + pub(crate) fn new(bits: u8) -> Self { + MODE_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<MODE_A> { + match self.bits { + 0 => Some(MODE_A::USART_EXT_CLK), + 1 => Some(MODE_A::USART_INT_CLK), + 2 => Some(MODE_A::SPI_SLAVE), + 3 => Some(MODE_A::SPI_MASTER), + 4 => Some(MODE_A::I2C_SLAVE), + 5 => Some(MODE_A::I2C_MASTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `USART_EXT_CLK`"] + #[inline(always)] + pub fn is_usart_ext_clk(&self) -> bool { + **self == MODE_A::USART_EXT_CLK + } + #[doc = "Checks if the value of the field is `USART_INT_CLK`"] + #[inline(always)] + pub fn is_usart_int_clk(&self) -> bool { + **self == MODE_A::USART_INT_CLK + } + #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[inline(always)] + pub fn is_spi_slave(&self) -> bool { + **self == MODE_A::SPI_SLAVE + } + #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[inline(always)] + pub fn is_spi_master(&self) -> bool { + **self == MODE_A::SPI_MASTER + } + #[doc = "Checks if the value of the field is `I2C_SLAVE`"] + #[inline(always)] + pub fn is_i2c_slave(&self) -> bool { + **self == MODE_A::I2C_SLAVE + } + #[doc = "Checks if the value of the field is `I2C_MASTER`"] + #[inline(always)] + pub fn is_i2c_master(&self) -> bool { + **self == MODE_A::I2C_MASTER + } +} +impl core::ops::Deref for MODE_R { + type Target = crate::FieldReader<u8, MODE_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub struct MODE_W<'a> { + w: &'a mut W, +} +impl<'a> MODE_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: MODE_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "USART with external clock"] + #[inline(always)] + pub fn usart_ext_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_EXT_CLK) + } + #[doc = "USART with internal clock"] + #[inline(always)] + pub fn usart_int_clk(self) -> &'a mut W { + self.variant(MODE_A::USART_INT_CLK) + } + #[doc = "SPI in slave operation"] + #[inline(always)] + pub fn spi_slave(self) -> &'a mut W { + self.variant(MODE_A::SPI_SLAVE) + } + #[doc = "SPI in master operation"] + #[inline(always)] + pub fn spi_master(self) -> &'a mut W { + self.variant(MODE_A::SPI_MASTER) + } + #[doc = "I2C slave operation"] + #[inline(always)] + pub fn i2c_slave(self) -> &'a mut W { + self.variant(MODE_A::I2C_SLAVE) + } + #[doc = "I2C master operation"] + #[inline(always)] + pub fn i2c_master(self) -> &'a mut W { + self.variant(MODE_A::I2C_MASTER) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x07 << 2)) | ((value as u32 & 0x07) << 2); + self.w + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>); +impl RUNSTDBY_R { + pub(crate) fn new(bits: bool) -> Self { + RUNSTDBY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RUNSTDBY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub struct RUNSTDBY_W<'a> { + w: &'a mut W, +} +impl<'a> RUNSTDBY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub struct PINOUT_R(crate::FieldReader<bool, bool>); +impl PINOUT_R { + pub(crate) fn new(bits: bool) -> Self { + PINOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PINOUT_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub struct PINOUT_W<'a> { + w: &'a mut W, +} +impl<'a> PINOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "SDA Hold Time\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SDAHOLD_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 50-100ns hold time"] + _75NS = 1, + #[doc = "2: 300-600ns hold time"] + _450NS = 2, + #[doc = "3: 400-800ns hold time"] + _600NS = 3, +} +impl From<SDAHOLD_A> for u8 { + #[inline(always)] + fn from(variant: SDAHOLD_A) -> Self { + variant as _ + } +} +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub struct SDAHOLD_R(crate::FieldReader<u8, SDAHOLD_A>); +impl SDAHOLD_R { + pub(crate) fn new(bits: u8) -> Self { + SDAHOLD_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SDAHOLD_A { + match self.bits { + 0 => SDAHOLD_A::DISABLE, + 1 => SDAHOLD_A::_75NS, + 2 => SDAHOLD_A::_450NS, + 3 => SDAHOLD_A::_600NS, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == SDAHOLD_A::DISABLE + } + #[doc = "Checks if the value of the field is `_75NS`"] + #[inline(always)] + pub fn is_75ns(&self) -> bool { + **self == SDAHOLD_A::_75NS + } + #[doc = "Checks if the value of the field is `_450NS`"] + #[inline(always)] + pub fn is_450ns(&self) -> bool { + **self == SDAHOLD_A::_450NS + } + #[doc = "Checks if the value of the field is `_600NS`"] + #[inline(always)] + pub fn is_600ns(&self) -> bool { + **self == SDAHOLD_A::_600NS + } +} +impl core::ops::Deref for SDAHOLD_R { + type Target = crate::FieldReader<u8, SDAHOLD_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub struct SDAHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> SDAHOLD_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SDAHOLD_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SDAHOLD_A::DISABLE) + } + #[doc = "50-100ns hold time"] + #[inline(always)] + pub fn _75ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_75NS) + } + #[doc = "300-600ns hold time"] + #[inline(always)] + pub fn _450ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_450NS) + } + #[doc = "400-800ns hold time"] + #[inline(always)] + pub fn _600ns(self) -> &'a mut W { + self.variant(SDAHOLD_A::_600NS) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 20)) | ((value as u32 & 0x03) << 20); + self.w + } +} +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_R(crate::FieldReader<bool, bool>); +impl MEXTTOEN_R { + pub(crate) fn new(bits: bool) -> Self { + MEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_R(crate::FieldReader<bool, bool>); +impl SEXTTOEN_R { + pub(crate) fn new(bits: bool) -> Self { + SEXTTOEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOEN_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +#[doc = "Transfer Speed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "0: Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz "] + STANDARD_AND_FAST_MODE = 0, + #[doc = "1: Fast-mode Plus Upto 1MHz"] + FASTPLUS_MODE = 1, + #[doc = "2: High-speed mode Upto 3.4MHz"] + HIGH_SPEED_MODE = 2, +} +impl From<SPEED_A> for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub struct SPEED_R(crate::FieldReader<u8, SPEED_A>); +impl SPEED_R { + pub(crate) fn new(bits: u8) -> Self { + SPEED_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<SPEED_A> { + match self.bits { + 0 => Some(SPEED_A::STANDARD_AND_FAST_MODE), + 1 => Some(SPEED_A::FASTPLUS_MODE), + 2 => Some(SPEED_A::HIGH_SPEED_MODE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STANDARD_AND_FAST_MODE`"] + #[inline(always)] + pub fn is_standard_and_fast_mode(&self) -> bool { + **self == SPEED_A::STANDARD_AND_FAST_MODE + } + #[doc = "Checks if the value of the field is `FASTPLUS_MODE`"] + #[inline(always)] + pub fn is_fastplus_mode(&self) -> bool { + **self == SPEED_A::FASTPLUS_MODE + } + #[doc = "Checks if the value of the field is `HIGH_SPEED_MODE`"] + #[inline(always)] + pub fn is_high_speed_mode(&self) -> bool { + **self == SPEED_A::HIGH_SPEED_MODE + } +} +impl core::ops::Deref for SPEED_R { + type Target = crate::FieldReader<u8, SPEED_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub struct SPEED_W<'a> { + w: &'a mut W, +} +impl<'a> SPEED_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: SPEED_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz"] + #[inline(always)] + pub fn standard_and_fast_mode(self) -> &'a mut W { + self.variant(SPEED_A::STANDARD_AND_FAST_MODE) + } + #[doc = "Fast-mode Plus Upto 1MHz"] + #[inline(always)] + pub fn fastplus_mode(self) -> &'a mut W { + self.variant(SPEED_A::FASTPLUS_MODE) + } + #[doc = "High-speed mode Upto 3.4MHz"] + #[inline(always)] + pub fn high_speed_mode(self) -> &'a mut W { + self.variant(SPEED_A::HIGH_SPEED_MODE) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24); + self.w + } +} +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub struct SCLSM_R(crate::FieldReader<bool, bool>); +impl SCLSM_R { + pub(crate) fn new(bits: bool) -> Self { + SCLSM_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SCLSM_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub struct SCLSM_W<'a> { + w: &'a mut W, +} +impl<'a> SCLSM_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27); + self.w + } +} +#[doc = "Inactive Time-Out\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum INACTOUT_A { + #[doc = "0: Disabled"] + DISABLE = 0, + #[doc = "1: 5-6 SCL Time-Out(50-60us)"] + _55US = 1, + #[doc = "2: 10-11 SCL Time-Out(100-110us)"] + _105US = 2, + #[doc = "3: 20-21 SCL Time-Out(200-210us)"] + _205US = 3, +} +impl From<INACTOUT_A> for u8 { + #[inline(always)] + fn from(variant: INACTOUT_A) -> Self { + variant as _ + } +} +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub struct INACTOUT_R(crate::FieldReader<u8, INACTOUT_A>); +impl INACTOUT_R { + pub(crate) fn new(bits: u8) -> Self { + INACTOUT_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INACTOUT_A { + match self.bits { + 0 => INACTOUT_A::DISABLE, + 1 => INACTOUT_A::_55US, + 2 => INACTOUT_A::_105US, + 3 => INACTOUT_A::_205US, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + **self == INACTOUT_A::DISABLE + } + #[doc = "Checks if the value of the field is `_55US`"] + #[inline(always)] + pub fn is_55us(&self) -> bool { + **self == INACTOUT_A::_55US + } + #[doc = "Checks if the value of the field is `_105US`"] + #[inline(always)] + pub fn is_105us(&self) -> bool { + **self == INACTOUT_A::_105US + } + #[doc = "Checks if the value of the field is `_205US`"] + #[inline(always)] + pub fn is_205us(&self) -> bool { + **self == INACTOUT_A::_205US + } +} +impl core::ops::Deref for INACTOUT_R { + type Target = crate::FieldReader<u8, INACTOUT_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub struct INACTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> INACTOUT_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: INACTOUT_A) -> &'a mut W { + self.bits(variant.into()) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(INACTOUT_A::DISABLE) + } + #[doc = "5-6 SCL Time-Out(50-60us)"] + #[inline(always)] + pub fn _55us(self) -> &'a mut W { + self.variant(INACTOUT_A::_55US) + } + #[doc = "10-11 SCL Time-Out(100-110us)"] + #[inline(always)] + pub fn _105us(self) -> &'a mut W { + self.variant(INACTOUT_A::_105US) + } + #[doc = "20-21 SCL Time-Out(200-210us)"] + #[inline(always)] + pub fn _205us(self) -> &'a mut W { + self.variant(INACTOUT_A::_205US) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28); + self.w + } +} +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_R(crate::FieldReader<bool, bool>); +impl LOWTOUTEN_R { + pub(crate) fn new(bits: bool) -> Self { + LOWTOUTEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUTEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub struct LOWTOUTEN_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUTEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30); + self.w + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 0x07) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 0x03) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 0x01) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 0x03) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 0x01) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 0x03) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&mut self) -> SWRST_W { + SWRST_W { w: self } + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W { w: self } + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&mut self) -> MODE_W { + MODE_W { w: self } + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&mut self) -> RUNSTDBY_W { + RUNSTDBY_W { w: self } + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&mut self) -> PINOUT_W { + PINOUT_W { w: self } + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&mut self) -> SDAHOLD_W { + SDAHOLD_W { w: self } + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&mut self) -> MEXTTOEN_W { + MEXTTOEN_W { w: self } + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&mut self) -> SEXTTOEN_W { + SEXTTOEN_W { w: self } + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W { w: self } + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&mut self) -> SCLSM_W { + SCLSM_W { w: self } + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&mut self) -> INACTOUT_W { + INACTOUT_W { w: self } + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W { + LOWTOUTEN_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/ctrlb.rs b/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 0000000..03070a3 --- /dev/null +++ b/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,240 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R<CTRLB_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CTRLB_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CTRLB_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W<CTRLB_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CTRLB_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CTRLB_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CTRLB_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub struct SMEN_R(crate::FieldReader<bool, bool>); +impl SMEN_R { + pub(crate) fn new(bits: bool) -> Self { + SMEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SMEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub struct SMEN_W<'a> { + w: &'a mut W, +} +impl<'a> SMEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub struct QCEN_R(crate::FieldReader<bool, bool>); +impl QCEN_R { + pub(crate) fn new(bits: bool) -> Self { + QCEN_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for QCEN_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub struct QCEN_W<'a> { + w: &'a mut W, +} +impl<'a> QCEN_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `CMD` reader - Command"] +pub struct CMD_R(crate::FieldReader<u8, u8>); +impl CMD_R { + pub(crate) fn new(bits: u8) -> Self { + CMD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CMD_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CMD` writer - Command"] +pub struct CMD_W<'a> { + w: &'a mut W, +} +impl<'a> CMD_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 16)) | ((value as u32 & 0x03) << 16); + self.w + } +} +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub struct ACKACT_R(crate::FieldReader<bool, bool>); +impl ACKACT_R { + pub(crate) fn new(bits: bool) -> Self { + ACKACT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ACKACT_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub struct ACKACT_W<'a> { + w: &'a mut W, +} +impl<'a> ACKACT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 16) & 0x03) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&mut self) -> SMEN_W { + SMEN_W { w: self } + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&mut self) -> QCEN_W { + QCEN_W { w: self } + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + pub fn cmd(&mut self) -> CMD_W { + CMD_W { w: self } + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&mut self) -> ACKACT_W { + ACKACT_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/data.rs b/src/sercom0/i2cm/data.rs new file mode 100644 index 0000000..f6a5b08 --- /dev/null +++ b/src/sercom0/i2cm/data.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R<DATA_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DATA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DATA_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DATA_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W<DATA_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DATA_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DATA_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DATA_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub struct DATA_R(crate::FieldReader<u8, u8>); +impl DATA_R { + pub(crate) fn new(bits: u8) -> Self { + DATA_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DATA_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DATA` writer - Data Value"] +pub struct DATA_W<'a> { + w: &'a mut W, +} +impl<'a> DATA_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u8 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&mut self) -> DATA_W { + DATA_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/dbgctrl.rs b/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 0000000..f4213b0 --- /dev/null +++ b/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,112 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R<DBGCTRL_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<DBGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<DBGCTRL_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<DBGCTRL_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W<DBGCTRL_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<DBGCTRL_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<DBGCTRL_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<DBGCTRL_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub struct DBGSTOP_R(crate::FieldReader<bool, bool>); +impl DBGSTOP_R { + pub(crate) fn new(bits: bool) -> Self { + DBGSTOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DBGSTOP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub struct DBGSTOP_W<'a> { + w: &'a mut W, +} +impl<'a> DBGSTOP_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&mut self) -> DBGSTOP_W { + DBGSTOP_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/intenclr.rs b/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 0000000..81b0874 --- /dev/null +++ b/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R<INTENCLR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENCLR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENCLR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W<INTENCLR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENCLR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENCLR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub struct MB_R(crate::FieldReader<bool, bool>); +impl MB_R { + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub struct SB_R(crate::FieldReader<bool, bool>); +impl SB_R { + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub struct ERROR_R(crate::FieldReader<bool, bool>); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/intenset.rs b/src/sercom0/i2cm/intenset.rs new file mode 100644 index 0000000..f763635 --- /dev/null +++ b/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R<INTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W<INTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub struct MB_R(crate::FieldReader<bool, bool>); +impl MB_R { + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub struct SB_R(crate::FieldReader<bool, bool>); +impl SB_R { + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub struct ERROR_R(crate::FieldReader<bool, bool>); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/intflag.rs b/src/sercom0/i2cm/intflag.rs new file mode 100644 index 0000000..36b65cc --- /dev/null +++ b/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R<INTFLAG_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTFLAG_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTFLAG_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W<INTFLAG_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTFLAG_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTFLAG_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub struct MB_R(crate::FieldReader<bool, bool>); +impl MB_R { + pub(crate) fn new(bits: bool) -> Self { + MB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub struct MB_W<'a> { + w: &'a mut W, +} +impl<'a> MB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub struct SB_R(crate::FieldReader<bool, bool>); +impl SB_R { + pub(crate) fn new(bits: bool) -> Self { + SB_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SB_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub struct SB_W<'a> { + w: &'a mut W, +} +impl<'a> SB_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1); + self.w + } +} +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub struct ERROR_R(crate::FieldReader<bool, bool>); +impl ERROR_R { + pub(crate) fn new(bits: bool) -> Self { + ERROR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ERROR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub struct ERROR_W<'a> { + w: &'a mut W, +} +impl<'a> ERROR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u8 & 0x01) << 7); + self.w + } +} +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&mut self) -> MB_W { + MB_W { w: self } + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&mut self) -> SB_W { + SB_W { w: self } + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&mut self) -> ERROR_W { + ERROR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/status.rs b/src/sercom0/i2cm/status.rs new file mode 100644 index 0000000..9089571 --- /dev/null +++ b/src/sercom0/i2cm/status.rs @@ -0,0 +1,470 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R<STATUS_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<STATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<STATUS_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<STATUS_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W<STATUS_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<STATUS_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<STATUS_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<STATUS_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub struct BUSERR_R(crate::FieldReader<bool, bool>); +impl BUSERR_R { + pub(crate) fn new(bits: bool) -> Self { + BUSERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSERR` writer - Bus Error"] +pub struct BUSERR_W<'a> { + w: &'a mut W, +} +impl<'a> BUSERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u16 & 0x01); + self.w + } +} +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub struct ARBLOST_R(crate::FieldReader<bool, bool>); +impl ARBLOST_R { + pub(crate) fn new(bits: bool) -> Self { + ARBLOST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ARBLOST_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub struct ARBLOST_W<'a> { + w: &'a mut W, +} +impl<'a> ARBLOST_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1); + self.w + } +} +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub struct RXNACK_R(crate::FieldReader<bool, bool>); +impl RXNACK_R { + pub(crate) fn new(bits: bool) -> Self { + RXNACK_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RXNACK_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RXNACK` writer - Received Not Acknowledge"] +pub struct RXNACK_W<'a> { + w: &'a mut W, +} +impl<'a> RXNACK_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2); + self.w + } +} +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub struct BUSSTATE_R(crate::FieldReader<u8, u8>); +impl BUSSTATE_R { + pub(crate) fn new(bits: u8) -> Self { + BUSSTATE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for BUSSTATE_R { + type Target = crate::FieldReader<u8, u8>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub struct BUSSTATE_W<'a> { + w: &'a mut W, +} +impl<'a> BUSSTATE_W<'a> { + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x03 << 4)) | ((value as u16 & 0x03) << 4); + self.w + } +} +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub struct LOWTOUT_R(crate::FieldReader<bool, bool>); +impl LOWTOUT_R { + pub(crate) fn new(bits: bool) -> Self { + LOWTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LOWTOUT_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub struct LOWTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> LOWTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6); + self.w + } +} +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub struct CLKHOLD_R(crate::FieldReader<bool, bool>); +impl CLKHOLD_R { + pub(crate) fn new(bits: bool) -> Self { + CLKHOLD_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKHOLD_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKHOLD` writer - Clock Hold"] +pub struct CLKHOLD_W<'a> { + w: &'a mut W, +} +impl<'a> CLKHOLD_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7); + self.w + } +} +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_R(crate::FieldReader<bool, bool>); +impl MEXTTOUT_R { + pub(crate) fn new(bits: bool) -> Self { + MEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MEXTTOUT_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub struct MEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> MEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8); + self.w + } +} +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_R(crate::FieldReader<bool, bool>); +impl SEXTTOUT_R { + pub(crate) fn new(bits: bool) -> Self { + SEXTTOUT_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SEXTTOUT_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub struct SEXTTOUT_W<'a> { + w: &'a mut W, +} +impl<'a> SEXTTOUT_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9); + self.w + } +} +#[doc = "Field `LENERR` reader - Length Error"] +pub struct LENERR_R(crate::FieldReader<bool, bool>); +impl LENERR_R { + pub(crate) fn new(bits: bool) -> Self { + LENERR_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for LENERR_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `LENERR` writer - Length Error"] +pub struct LENERR_W<'a> { + w: &'a mut W, +} +impl<'a> LENERR_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u16 & 0x01) << 10); + self.w + } +} +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 0x03) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&mut self) -> BUSERR_W { + BUSERR_W { w: self } + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&mut self) -> ARBLOST_W { + ARBLOST_W { w: self } + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&mut self) -> RXNACK_W { + RXNACK_W { w: self } + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&mut self) -> BUSSTATE_W { + BUSSTATE_W { w: self } + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&mut self) -> LOWTOUT_W { + LOWTOUT_W { w: self } + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&mut self) -> CLKHOLD_W { + CLKHOLD_W { w: self } + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&mut self) -> MEXTTOUT_W { + MEXTTOUT_W { w: self } + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&mut self) -> SEXTTOUT_W { + SEXTTOUT_W { w: self } + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&mut self) -> LENERR_W { + LENERR_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/sercom0/i2cm/syncbusy.rs b/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 0000000..57289aa --- /dev/null +++ b/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,90 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R<SYNCBUSY_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<SYNCBUSY_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<SYNCBUSY_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<SYNCBUSY_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub struct SWRST_R(crate::FieldReader<bool, bool>); +impl SWRST_R { + pub(crate) fn new(bits: bool) -> Self { + SWRST_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SWRST_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub struct ENABLE_R(crate::FieldReader<bool, bool>); +impl ENABLE_R { + pub(crate) fn new(bits: bool) -> Self { + ENABLE_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ENABLE_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub struct SYSOP_R(crate::FieldReader<bool, bool>); +impl SYSOP_R { + pub(crate) fn new(bits: bool) -> Self { + SYSOP_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SYSOP_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} |