diff options
Diffstat (limited to 'src/osc32kctrl/intenset.rs')
| -rw-r--r-- | src/osc32kctrl/intenset.rs | 204 |
1 files changed, 204 insertions, 0 deletions
diff --git a/src/osc32kctrl/intenset.rs b/src/osc32kctrl/intenset.rs new file mode 100644 index 0000000..d1d4f7b --- /dev/null +++ b/src/osc32kctrl/intenset.rs @@ -0,0 +1,204 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R<INTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W<INTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_R(crate::FieldReader<bool, bool>); +impl XOSC32KRDY_R { + pub(crate) fn new(bits: bool) -> Self { + XOSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for XOSC32KRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub struct XOSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> XOSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_R(crate::FieldReader<bool, bool>); +impl OSC32KRDY_R { + pub(crate) fn new(bits: bool) -> Self { + OSC32KRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"] +pub struct OSC32KRDY_W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_R(crate::FieldReader<bool, bool>); +impl CLKFAIL_R { + pub(crate) fn new(bits: bool) -> Self { + CLKFAIL_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CLKFAIL_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub struct CLKFAIL_W<'a> { + w: &'a mut W, +} +impl<'a> CLKFAIL_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&self) -> OSC32KRDY_R { + OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W { + XOSC32KRDY_W { w: self } + } + #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn osc32krdy(&mut self) -> OSC32KRDY_W { + OSC32KRDY_W { w: self } + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&mut self) -> CLKFAIL_W { + CLKFAIL_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} |