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-rw-r--r--src/osc32kctrl/cfdctrl.rs204
-rw-r--r--src/osc32kctrl/evctrl.rs112
-rw-r--r--src/osc32kctrl/intenclr.rs204
-rw-r--r--src/osc32kctrl/intenset.rs204
-rw-r--r--src/osc32kctrl/intflag.rs204
-rw-r--r--src/osc32kctrl/osc32k.rs541
-rw-r--r--src/osc32kctrl/osculp32k.rs148
-rw-r--r--src/osc32kctrl/rtcctrl.rs203
-rw-r--r--src/osc32kctrl/status.rs109
-rw-r--r--src/osc32kctrl/xosc32k.rs551
10 files changed, 2480 insertions, 0 deletions
diff --git a/src/osc32kctrl/cfdctrl.rs b/src/osc32kctrl/cfdctrl.rs
new file mode 100644
index 0000000..8695190
--- /dev/null
+++ b/src/osc32kctrl/cfdctrl.rs
@@ -0,0 +1,204 @@
+#[doc = "Register `CFDCTRL` reader"]
+pub struct R(crate::R<CFDCTRL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<CFDCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<CFDCTRL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<CFDCTRL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `CFDCTRL` writer"]
+pub struct W(crate::W<CFDCTRL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<CFDCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<CFDCTRL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<CFDCTRL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"]
+pub struct CFDEN_R(crate::FieldReader<bool, bool>);
+impl CFDEN_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CFDEN_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CFDEN_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"]
+pub struct CFDEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CFDEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `SWBACK` reader - Clock Switch Back"]
+pub struct SWBACK_R(crate::FieldReader<bool, bool>);
+impl SWBACK_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ SWBACK_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for SWBACK_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `SWBACK` writer - Clock Switch Back"]
+pub struct SWBACK_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SWBACK_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"]
+pub struct CFDPRESC_R(crate::FieldReader<bool, bool>);
+impl CFDPRESC_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CFDPRESC_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CFDPRESC_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"]
+pub struct CFDPRESC_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CFDPRESC_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - Clock Failure Detector Enable"]
+ #[inline(always)]
+ pub fn cfden(&self) -> CFDEN_R {
+ CFDEN_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - Clock Switch Back"]
+ #[inline(always)]
+ pub fn swback(&self) -> SWBACK_R {
+ SWBACK_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - Clock Failure Detector Prescaler"]
+ #[inline(always)]
+ pub fn cfdpresc(&self) -> CFDPRESC_R {
+ CFDPRESC_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Clock Failure Detector Enable"]
+ #[inline(always)]
+ pub fn cfden(&mut self) -> CFDEN_W {
+ CFDEN_W { w: self }
+ }
+ #[doc = "Bit 1 - Clock Switch Back"]
+ #[inline(always)]
+ pub fn swback(&mut self) -> SWBACK_W {
+ SWBACK_W { w: self }
+ }
+ #[doc = "Bit 2 - Clock Failure Detector Prescaler"]
+ #[inline(always)]
+ pub fn cfdpresc(&mut self) -> CFDPRESC_W {
+ CFDPRESC_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"]
+pub struct CFDCTRL_SPEC;
+impl crate::RegisterSpec for CFDCTRL_SPEC {
+ type Ux = u8;
+}
+#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"]
+impl crate::Readable for CFDCTRL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"]
+impl crate::Writable for CFDCTRL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets CFDCTRL to value 0"]
+impl crate::Resettable for CFDCTRL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/evctrl.rs b/src/osc32kctrl/evctrl.rs
new file mode 100644
index 0000000..bd47766
--- /dev/null
+++ b/src/osc32kctrl/evctrl.rs
@@ -0,0 +1,112 @@
+#[doc = "Register `EVCTRL` reader"]
+pub struct R(crate::R<EVCTRL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<EVCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<EVCTRL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<EVCTRL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `EVCTRL` writer"]
+pub struct W(crate::W<EVCTRL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<EVCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<EVCTRL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<EVCTRL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"]
+pub struct CFDEO_R(crate::FieldReader<bool, bool>);
+impl CFDEO_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CFDEO_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CFDEO_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"]
+pub struct CFDEO_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CFDEO_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"]
+ #[inline(always)]
+ pub fn cfdeo(&self) -> CFDEO_R {
+ CFDEO_R::new((self.bits & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"]
+ #[inline(always)]
+ pub fn cfdeo(&mut self) -> CFDEO_W {
+ CFDEO_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"]
+pub struct EVCTRL_SPEC;
+impl crate::RegisterSpec for EVCTRL_SPEC {
+ type Ux = u8;
+}
+#[doc = "`read()` method returns [evctrl::R](R) reader structure"]
+impl crate::Readable for EVCTRL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"]
+impl crate::Writable for EVCTRL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets EVCTRL to value 0"]
+impl crate::Resettable for EVCTRL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/intenclr.rs b/src/osc32kctrl/intenclr.rs
new file mode 100644
index 0000000..821c3c6
--- /dev/null
+++ b/src/osc32kctrl/intenclr.rs
@@ -0,0 +1,204 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<INTENCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<INTENCLR_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"]
+pub struct XOSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl XOSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ XOSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for XOSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"]
+pub struct XOSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> XOSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"]
+pub struct OSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl OSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ OSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for OSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"]
+pub struct OSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> OSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"]
+pub struct CLKFAIL_R(crate::FieldReader<bool, bool>);
+impl CLKFAIL_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CLKFAIL_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CLKFAIL_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"]
+pub struct CLKFAIL_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CLKFAIL_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn xosc32krdy(&self) -> XOSC32KRDY_R {
+ XOSC32KRDY_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn osc32krdy(&self) -> OSC32KRDY_R {
+ OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
+ #[inline(always)]
+ pub fn clkfail(&self) -> CLKFAIL_R {
+ CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W {
+ XOSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn osc32krdy(&mut self) -> OSC32KRDY_W {
+ OSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
+ #[inline(always)]
+ pub fn clkfail(&mut self) -> CLKFAIL_W {
+ CLKFAIL_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/intenset.rs b/src/osc32kctrl/intenset.rs
new file mode 100644
index 0000000..d1d4f7b
--- /dev/null
+++ b/src/osc32kctrl/intenset.rs
@@ -0,0 +1,204 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<INTENSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<INTENSET_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"]
+pub struct XOSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl XOSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ XOSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for XOSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"]
+pub struct XOSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> XOSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"]
+pub struct OSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl OSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ OSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for OSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"]
+pub struct OSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> OSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"]
+pub struct CLKFAIL_R(crate::FieldReader<bool, bool>);
+impl CLKFAIL_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CLKFAIL_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CLKFAIL_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"]
+pub struct CLKFAIL_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CLKFAIL_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn xosc32krdy(&self) -> XOSC32KRDY_R {
+ XOSC32KRDY_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn osc32krdy(&self) -> OSC32KRDY_R {
+ OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
+ #[inline(always)]
+ pub fn clkfail(&self) -> CLKFAIL_R {
+ CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W {
+ XOSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 1 - OSC32K Ready Interrupt Enable"]
+ #[inline(always)]
+ pub fn osc32krdy(&mut self) -> OSC32KRDY_W {
+ OSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"]
+ #[inline(always)]
+ pub fn clkfail(&mut self) -> CLKFAIL_W {
+ CLKFAIL_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/intflag.rs b/src/osc32kctrl/intflag.rs
new file mode 100644
index 0000000..d86a318
--- /dev/null
+++ b/src/osc32kctrl/intflag.rs
@@ -0,0 +1,204 @@
+#[doc = "Register `INTFLAG` reader"]
+pub struct R(crate::R<INTFLAG_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<INTFLAG_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<INTFLAG_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<INTFLAG_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `INTFLAG` writer"]
+pub struct W(crate::W<INTFLAG_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<INTFLAG_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<INTFLAG_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<INTFLAG_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"]
+pub struct XOSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl XOSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ XOSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for XOSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"]
+pub struct XOSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> XOSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"]
+pub struct OSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl OSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ OSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for OSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `OSC32KRDY` writer - OSC32K Ready"]
+pub struct OSC32KRDY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> OSC32KRDY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"]
+pub struct CLKFAIL_R(crate::FieldReader<bool, bool>);
+impl CLKFAIL_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CLKFAIL_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CLKFAIL_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"]
+pub struct CLKFAIL_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CLKFAIL_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - XOSC32K Ready"]
+ #[inline(always)]
+ pub fn xosc32krdy(&self) -> XOSC32KRDY_R {
+ XOSC32KRDY_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - OSC32K Ready"]
+ #[inline(always)]
+ pub fn osc32krdy(&self) -> OSC32KRDY_R {
+ OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector"]
+ #[inline(always)]
+ pub fn clkfail(&self) -> CLKFAIL_R {
+ CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - XOSC32K Ready"]
+ #[inline(always)]
+ pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W {
+ XOSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 1 - OSC32K Ready"]
+ #[inline(always)]
+ pub fn osc32krdy(&mut self) -> OSC32KRDY_W {
+ OSC32KRDY_W { w: self }
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector"]
+ #[inline(always)]
+ pub fn clkfail(&mut self) -> CLKFAIL_W {
+ CLKFAIL_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"]
+pub struct INTFLAG_SPEC;
+impl crate::RegisterSpec for INTFLAG_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [intflag::R](R) reader structure"]
+impl crate::Readable for INTFLAG_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"]
+impl crate::Writable for INTFLAG_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets INTFLAG to value 0"]
+impl crate::Resettable for INTFLAG_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/osc32k.rs b/src/osc32kctrl/osc32k.rs
new file mode 100644
index 0000000..fd55fd4
--- /dev/null
+++ b/src/osc32kctrl/osc32k.rs
@@ -0,0 +1,541 @@
+#[doc = "Register `OSC32K` reader"]
+pub struct R(crate::R<OSC32K_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OSC32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OSC32K_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OSC32K_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OSC32K` writer"]
+pub struct W(crate::W<OSC32K_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OSC32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OSC32K_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OSC32K_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `ENABLE` reader - Oscillator Enable"]
+pub struct ENABLE_R(crate::FieldReader<bool, bool>);
+impl ENABLE_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ ENABLE_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for ENABLE_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `ENABLE` writer - Oscillator Enable"]
+pub struct ENABLE_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ENABLE_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `EN32K` reader - 32kHz Output Enable"]
+pub struct EN32K_R(crate::FieldReader<bool, bool>);
+impl EN32K_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ EN32K_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EN32K_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EN32K` writer - 32kHz Output Enable"]
+pub struct EN32K_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EN32K_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+ self.w
+ }
+}
+#[doc = "Field `EN1K` reader - 1kHz Output Enable"]
+pub struct EN1K_R(crate::FieldReader<bool, bool>);
+impl EN1K_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ EN1K_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EN1K_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EN1K` writer - 1kHz Output Enable"]
+pub struct EN1K_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EN1K_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
+ self.w
+ }
+}
+#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
+pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>);
+impl RUNSTDBY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ RUNSTDBY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for RUNSTDBY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
+pub struct RUNSTDBY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> RUNSTDBY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+ self.w
+ }
+}
+#[doc = "Field `ONDEMAND` reader - On Demand Control"]
+pub struct ONDEMAND_R(crate::FieldReader<bool, bool>);
+impl ONDEMAND_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ ONDEMAND_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for ONDEMAND_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `ONDEMAND` writer - On Demand Control"]
+pub struct ONDEMAND_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ONDEMAND_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
+ self.w
+ }
+}
+#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum STARTUP_A {
+ #[doc = "0: 0.092 ms"]
+ CYCLE3 = 0,
+ #[doc = "1: 0.122 ms"]
+ CYCLE4 = 1,
+ #[doc = "2: 0.183 ms"]
+ CYCLE6 = 2,
+ #[doc = "3: 0.305 ms"]
+ CYCLE10 = 3,
+ #[doc = "4: 0.549 ms"]
+ CYCLE18 = 4,
+ #[doc = "5: 1.038 ms"]
+ CYCLE34 = 5,
+ #[doc = "6: 2.014 ms"]
+ CYCLE66 = 6,
+ #[doc = "7: 3.967 ms"]
+ CYCLE130 = 7,
+}
+impl From<STARTUP_A> for u8 {
+ #[inline(always)]
+ fn from(variant: STARTUP_A) -> Self {
+ variant as _
+ }
+}
+#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"]
+pub struct STARTUP_R(crate::FieldReader<u8, STARTUP_A>);
+impl STARTUP_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ STARTUP_R(crate::FieldReader::new(bits))
+ }
+ #[doc = r"Get enumerated values variant"]
+ #[inline(always)]
+ pub fn variant(&self) -> STARTUP_A {
+ match self.bits {
+ 0 => STARTUP_A::CYCLE3,
+ 1 => STARTUP_A::CYCLE4,
+ 2 => STARTUP_A::CYCLE6,
+ 3 => STARTUP_A::CYCLE10,
+ 4 => STARTUP_A::CYCLE18,
+ 5 => STARTUP_A::CYCLE34,
+ 6 => STARTUP_A::CYCLE66,
+ 7 => STARTUP_A::CYCLE130,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Checks if the value of the field is `CYCLE3`"]
+ #[inline(always)]
+ pub fn is_cycle3(&self) -> bool {
+ **self == STARTUP_A::CYCLE3
+ }
+ #[doc = "Checks if the value of the field is `CYCLE4`"]
+ #[inline(always)]
+ pub fn is_cycle4(&self) -> bool {
+ **self == STARTUP_A::CYCLE4
+ }
+ #[doc = "Checks if the value of the field is `CYCLE6`"]
+ #[inline(always)]
+ pub fn is_cycle6(&self) -> bool {
+ **self == STARTUP_A::CYCLE6
+ }
+ #[doc = "Checks if the value of the field is `CYCLE10`"]
+ #[inline(always)]
+ pub fn is_cycle10(&self) -> bool {
+ **self == STARTUP_A::CYCLE10
+ }
+ #[doc = "Checks if the value of the field is `CYCLE18`"]
+ #[inline(always)]
+ pub fn is_cycle18(&self) -> bool {
+ **self == STARTUP_A::CYCLE18
+ }
+ #[doc = "Checks if the value of the field is `CYCLE34`"]
+ #[inline(always)]
+ pub fn is_cycle34(&self) -> bool {
+ **self == STARTUP_A::CYCLE34
+ }
+ #[doc = "Checks if the value of the field is `CYCLE66`"]
+ #[inline(always)]
+ pub fn is_cycle66(&self) -> bool {
+ **self == STARTUP_A::CYCLE66
+ }
+ #[doc = "Checks if the value of the field is `CYCLE130`"]
+ #[inline(always)]
+ pub fn is_cycle130(&self) -> bool {
+ **self == STARTUP_A::CYCLE130
+ }
+}
+impl core::ops::Deref for STARTUP_R {
+ type Target = crate::FieldReader<u8, STARTUP_A>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"]
+pub struct STARTUP_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> STARTUP_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: STARTUP_A) -> &'a mut W {
+ self.bits(variant.into())
+ }
+ #[doc = "0.092 ms"]
+ #[inline(always)]
+ pub fn cycle3(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE3)
+ }
+ #[doc = "0.122 ms"]
+ #[inline(always)]
+ pub fn cycle4(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE4)
+ }
+ #[doc = "0.183 ms"]
+ #[inline(always)]
+ pub fn cycle6(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE6)
+ }
+ #[doc = "0.305 ms"]
+ #[inline(always)]
+ pub fn cycle10(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE10)
+ }
+ #[doc = "0.549 ms"]
+ #[inline(always)]
+ pub fn cycle18(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE18)
+ }
+ #[doc = "1.038 ms"]
+ #[inline(always)]
+ pub fn cycle34(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE34)
+ }
+ #[doc = "2.014 ms"]
+ #[inline(always)]
+ pub fn cycle66(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE66)
+ }
+ #[doc = "3.967 ms"]
+ #[inline(always)]
+ pub fn cycle130(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE130)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u32 & 0x07) << 8);
+ self.w
+ }
+}
+#[doc = "Field `WRTLOCK` reader - Write Lock"]
+pub struct WRTLOCK_R(crate::FieldReader<bool, bool>);
+impl WRTLOCK_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ WRTLOCK_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for WRTLOCK_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `WRTLOCK` writer - Write Lock"]
+pub struct WRTLOCK_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> WRTLOCK_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
+ self.w
+ }
+}
+#[doc = "Field `CALIB` reader - Oscillator Calibration"]
+pub struct CALIB_R(crate::FieldReader<u8, u8>);
+impl CALIB_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ CALIB_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CALIB_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CALIB` writer - Oscillator Calibration"]
+pub struct CALIB_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CALIB_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x7f << 16)) | ((value as u32 & 0x7f) << 16);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 1 - Oscillator Enable"]
+ #[inline(always)]
+ pub fn enable(&self) -> ENABLE_R {
+ ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - 32kHz Output Enable"]
+ #[inline(always)]
+ pub fn en32k(&self) -> EN32K_R {
+ EN32K_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+ #[doc = "Bit 3 - 1kHz Output Enable"]
+ #[inline(always)]
+ pub fn en1k(&self) -> EN1K_R {
+ EN1K_R::new(((self.bits >> 3) & 0x01) != 0)
+ }
+ #[doc = "Bit 6 - Run in Standby"]
+ #[inline(always)]
+ pub fn runstdby(&self) -> RUNSTDBY_R {
+ RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0)
+ }
+ #[doc = "Bit 7 - On Demand Control"]
+ #[inline(always)]
+ pub fn ondemand(&self) -> ONDEMAND_R {
+ ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0)
+ }
+ #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
+ #[inline(always)]
+ pub fn startup(&self) -> STARTUP_R {
+ STARTUP_R::new(((self.bits >> 8) & 0x07) as u8)
+ }
+ #[doc = "Bit 12 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&self) -> WRTLOCK_R {
+ WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0)
+ }
+ #[doc = "Bits 16:22 - Oscillator Calibration"]
+ #[inline(always)]
+ pub fn calib(&self) -> CALIB_R {
+ CALIB_R::new(((self.bits >> 16) & 0x7f) as u8)
+ }
+}
+impl W {
+ #[doc = "Bit 1 - Oscillator Enable"]
+ #[inline(always)]
+ pub fn enable(&mut self) -> ENABLE_W {
+ ENABLE_W { w: self }
+ }
+ #[doc = "Bit 2 - 32kHz Output Enable"]
+ #[inline(always)]
+ pub fn en32k(&mut self) -> EN32K_W {
+ EN32K_W { w: self }
+ }
+ #[doc = "Bit 3 - 1kHz Output Enable"]
+ #[inline(always)]
+ pub fn en1k(&mut self) -> EN1K_W {
+ EN1K_W { w: self }
+ }
+ #[doc = "Bit 6 - Run in Standby"]
+ #[inline(always)]
+ pub fn runstdby(&mut self) -> RUNSTDBY_W {
+ RUNSTDBY_W { w: self }
+ }
+ #[doc = "Bit 7 - On Demand Control"]
+ #[inline(always)]
+ pub fn ondemand(&mut self) -> ONDEMAND_W {
+ ONDEMAND_W { w: self }
+ }
+ #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
+ #[inline(always)]
+ pub fn startup(&mut self) -> STARTUP_W {
+ STARTUP_W { w: self }
+ }
+ #[doc = "Bit 12 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&mut self) -> WRTLOCK_W {
+ WRTLOCK_W { w: self }
+ }
+ #[doc = "Bits 16:22 - Oscillator Calibration"]
+ #[inline(always)]
+ pub fn calib(&mut self) -> CALIB_W {
+ CALIB_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "32kHz Internal Oscillator (OSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc32k](index.html) module"]
+pub struct OSC32K_SPEC;
+impl crate::RegisterSpec for OSC32K_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [osc32k::R](R) reader structure"]
+impl crate::Readable for OSC32K_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [osc32k::W](W) writer structure"]
+impl crate::Writable for OSC32K_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OSC32K to value 0x003f_0080"]
+impl crate::Resettable for OSC32K_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0x003f_0080
+ }
+}
diff --git a/src/osc32kctrl/osculp32k.rs b/src/osc32kctrl/osculp32k.rs
new file mode 100644
index 0000000..f6361ba
--- /dev/null
+++ b/src/osc32kctrl/osculp32k.rs
@@ -0,0 +1,148 @@
+#[doc = "Register `OSCULP32K` reader"]
+pub struct R(crate::R<OSCULP32K_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<OSCULP32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<OSCULP32K_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<OSCULP32K_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `OSCULP32K` writer"]
+pub struct W(crate::W<OSCULP32K_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<OSCULP32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<OSCULP32K_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<OSCULP32K_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `CALIB` reader - Oscillator Calibration"]
+pub struct CALIB_R(crate::FieldReader<u8, u8>);
+impl CALIB_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ CALIB_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CALIB_R {
+ type Target = crate::FieldReader<u8, u8>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CALIB` writer - Oscillator Calibration"]
+pub struct CALIB_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> CALIB_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x1f << 8)) | ((value as u32 & 0x1f) << 8);
+ self.w
+ }
+}
+#[doc = "Field `WRTLOCK` reader - Write Lock"]
+pub struct WRTLOCK_R(crate::FieldReader<bool, bool>);
+impl WRTLOCK_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ WRTLOCK_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for WRTLOCK_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `WRTLOCK` writer - Write Lock"]
+pub struct WRTLOCK_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> WRTLOCK_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bits 8:12 - Oscillator Calibration"]
+ #[inline(always)]
+ pub fn calib(&self) -> CALIB_R {
+ CALIB_R::new(((self.bits >> 8) & 0x1f) as u8)
+ }
+ #[doc = "Bit 15 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&self) -> WRTLOCK_R {
+ WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 8:12 - Oscillator Calibration"]
+ #[inline(always)]
+ pub fn calib(&mut self) -> CALIB_W {
+ CALIB_W { w: self }
+ }
+ #[doc = "Bit 15 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&mut self) -> WRTLOCK_W {
+ WRTLOCK_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"]
+pub struct OSCULP32K_SPEC;
+impl crate::RegisterSpec for OSCULP32K_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [osculp32k::R](R) reader structure"]
+impl crate::Readable for OSCULP32K_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"]
+impl crate::Writable for OSCULP32K_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets OSCULP32K to value 0"]
+impl crate::Resettable for OSCULP32K_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/rtcctrl.rs b/src/osc32kctrl/rtcctrl.rs
new file mode 100644
index 0000000..5e6f401
--- /dev/null
+++ b/src/osc32kctrl/rtcctrl.rs
@@ -0,0 +1,203 @@
+#[doc = "Register `RTCCTRL` reader"]
+pub struct R(crate::R<RTCCTRL_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<RTCCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<RTCCTRL_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<RTCCTRL_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `RTCCTRL` writer"]
+pub struct W(crate::W<RTCCTRL_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<RTCCTRL_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<RTCCTRL_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<RTCCTRL_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "RTC Clock Selection\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum RTCSEL_A {
+ #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"]
+ ULP1K = 0,
+ #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"]
+ ULP32K = 1,
+ #[doc = "2: 1.024kHz from 32.768kHz internal oscillator"]
+ OSC1K = 2,
+ #[doc = "3: 32.768kHz from 32.768kHz internal oscillator"]
+ OSC32K = 3,
+ #[doc = "4: 1.024kHz from 32.768kHz internal oscillator"]
+ XOSC1K = 4,
+ #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"]
+ XOSC32K = 5,
+}
+impl From<RTCSEL_A> for u8 {
+ #[inline(always)]
+ fn from(variant: RTCSEL_A) -> Self {
+ variant as _
+ }
+}
+#[doc = "Field `RTCSEL` reader - RTC Clock Selection"]
+pub struct RTCSEL_R(crate::FieldReader<u8, RTCSEL_A>);
+impl RTCSEL_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ RTCSEL_R(crate::FieldReader::new(bits))
+ }
+ #[doc = r"Get enumerated values variant"]
+ #[inline(always)]
+ pub fn variant(&self) -> Option<RTCSEL_A> {
+ match self.bits {
+ 0 => Some(RTCSEL_A::ULP1K),
+ 1 => Some(RTCSEL_A::ULP32K),
+ 2 => Some(RTCSEL_A::OSC1K),
+ 3 => Some(RTCSEL_A::OSC32K),
+ 4 => Some(RTCSEL_A::XOSC1K),
+ 5 => Some(RTCSEL_A::XOSC32K),
+ _ => None,
+ }
+ }
+ #[doc = "Checks if the value of the field is `ULP1K`"]
+ #[inline(always)]
+ pub fn is_ulp1k(&self) -> bool {
+ **self == RTCSEL_A::ULP1K
+ }
+ #[doc = "Checks if the value of the field is `ULP32K`"]
+ #[inline(always)]
+ pub fn is_ulp32k(&self) -> bool {
+ **self == RTCSEL_A::ULP32K
+ }
+ #[doc = "Checks if the value of the field is `OSC1K`"]
+ #[inline(always)]
+ pub fn is_osc1k(&self) -> bool {
+ **self == RTCSEL_A::OSC1K
+ }
+ #[doc = "Checks if the value of the field is `OSC32K`"]
+ #[inline(always)]
+ pub fn is_osc32k(&self) -> bool {
+ **self == RTCSEL_A::OSC32K
+ }
+ #[doc = "Checks if the value of the field is `XOSC1K`"]
+ #[inline(always)]
+ pub fn is_xosc1k(&self) -> bool {
+ **self == RTCSEL_A::XOSC1K
+ }
+ #[doc = "Checks if the value of the field is `XOSC32K`"]
+ #[inline(always)]
+ pub fn is_xosc32k(&self) -> bool {
+ **self == RTCSEL_A::XOSC32K
+ }
+}
+impl core::ops::Deref for RTCSEL_R {
+ type Target = crate::FieldReader<u8, RTCSEL_A>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `RTCSEL` writer - RTC Clock Selection"]
+pub struct RTCSEL_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> RTCSEL_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: RTCSEL_A) -> &'a mut W {
+ unsafe { self.bits(variant.into()) }
+ }
+ #[doc = "1.024kHz from 32kHz internal ULP oscillator"]
+ #[inline(always)]
+ pub fn ulp1k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::ULP1K)
+ }
+ #[doc = "32.768kHz from 32kHz internal ULP oscillator"]
+ #[inline(always)]
+ pub fn ulp32k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::ULP32K)
+ }
+ #[doc = "1.024kHz from 32.768kHz internal oscillator"]
+ #[inline(always)]
+ pub fn osc1k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::OSC1K)
+ }
+ #[doc = "32.768kHz from 32.768kHz internal oscillator"]
+ #[inline(always)]
+ pub fn osc32k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::OSC32K)
+ }
+ #[doc = "1.024kHz from 32.768kHz internal oscillator"]
+ #[inline(always)]
+ pub fn xosc1k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::XOSC1K)
+ }
+ #[doc = "32.768kHz from 32.768kHz external crystal oscillator"]
+ #[inline(always)]
+ pub fn xosc32k(self) -> &'a mut W {
+ self.variant(RTCSEL_A::XOSC32K)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bits 0:2 - RTC Clock Selection"]
+ #[inline(always)]
+ pub fn rtcsel(&self) -> RTCSEL_R {
+ RTCSEL_R::new((self.bits & 0x07) as u8)
+ }
+}
+impl W {
+ #[doc = "Bits 0:2 - RTC Clock Selection"]
+ #[inline(always)]
+ pub fn rtcsel(&mut self) -> RTCSEL_W {
+ RTCSEL_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "Clock selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"]
+pub struct RTCCTRL_SPEC;
+impl crate::RegisterSpec for RTCCTRL_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"]
+impl crate::Readable for RTCCTRL_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"]
+impl crate::Writable for RTCCTRL_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets RTCCTRL to value 0"]
+impl crate::Resettable for RTCCTRL_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/status.rs b/src/osc32kctrl/status.rs
new file mode 100644
index 0000000..029af30
--- /dev/null
+++ b/src/osc32kctrl/status.rs
@@ -0,0 +1,109 @@
+#[doc = "Register `STATUS` reader"]
+pub struct R(crate::R<STATUS_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<STATUS_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<STATUS_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<STATUS_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"]
+pub struct XOSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl XOSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ XOSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for XOSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `OSC32KRDY` reader - OSC32K Ready"]
+pub struct OSC32KRDY_R(crate::FieldReader<bool, bool>);
+impl OSC32KRDY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ OSC32KRDY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for OSC32KRDY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"]
+pub struct CLKFAIL_R(crate::FieldReader<bool, bool>);
+impl CLKFAIL_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CLKFAIL_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CLKFAIL_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"]
+pub struct CLKSW_R(crate::FieldReader<bool, bool>);
+impl CLKSW_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ CLKSW_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for CLKSW_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl R {
+ #[doc = "Bit 0 - XOSC32K Ready"]
+ #[inline(always)]
+ pub fn xosc32krdy(&self) -> XOSC32KRDY_R {
+ XOSC32KRDY_R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - OSC32K Ready"]
+ #[inline(always)]
+ pub fn osc32krdy(&self) -> OSC32KRDY_R {
+ OSC32KRDY_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - XOSC32K Clock Failure Detector"]
+ #[inline(always)]
+ pub fn clkfail(&self) -> CLKFAIL_R {
+ CLKFAIL_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+ #[doc = "Bit 3 - XOSC32K Clock switch"]
+ #[inline(always)]
+ pub fn clksw(&self) -> CLKSW_R {
+ CLKSW_R::new(((self.bits >> 3) & 0x01) != 0)
+ }
+}
+#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [status::R](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {
+ type Reader = R;
+}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0
+ }
+}
diff --git a/src/osc32kctrl/xosc32k.rs b/src/osc32kctrl/xosc32k.rs
new file mode 100644
index 0000000..bc9dfc5
--- /dev/null
+++ b/src/osc32kctrl/xosc32k.rs
@@ -0,0 +1,551 @@
+#[doc = "Register `XOSC32K` reader"]
+pub struct R(crate::R<XOSC32K_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<XOSC32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<XOSC32K_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<XOSC32K_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `XOSC32K` writer"]
+pub struct W(crate::W<XOSC32K_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<XOSC32K_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<XOSC32K_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<XOSC32K_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `ENABLE` reader - Oscillator Enable"]
+pub struct ENABLE_R(crate::FieldReader<bool, bool>);
+impl ENABLE_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ ENABLE_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for ENABLE_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `ENABLE` writer - Oscillator Enable"]
+pub struct ENABLE_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ENABLE_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u16 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"]
+pub struct XTALEN_R(crate::FieldReader<bool, bool>);
+impl XTALEN_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ XTALEN_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for XTALEN_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"]
+pub struct XTALEN_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> XTALEN_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2);
+ self.w
+ }
+}
+#[doc = "Field `EN32K` reader - 32kHz Output Enable"]
+pub struct EN32K_R(crate::FieldReader<bool, bool>);
+impl EN32K_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ EN32K_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EN32K_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EN32K` writer - 32kHz Output Enable"]
+pub struct EN32K_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EN32K_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3);
+ self.w
+ }
+}
+#[doc = "Field `EN1K` reader - 1kHz Output Enable"]
+pub struct EN1K_R(crate::FieldReader<bool, bool>);
+impl EN1K_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ EN1K_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for EN1K_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `EN1K` writer - 1kHz Output Enable"]
+pub struct EN1K_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EN1K_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4);
+ self.w
+ }
+}
+#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
+pub struct RUNSTDBY_R(crate::FieldReader<bool, bool>);
+impl RUNSTDBY_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ RUNSTDBY_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for RUNSTDBY_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
+pub struct RUNSTDBY_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> RUNSTDBY_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6);
+ self.w
+ }
+}
+#[doc = "Field `ONDEMAND` reader - On Demand Control"]
+pub struct ONDEMAND_R(crate::FieldReader<bool, bool>);
+impl ONDEMAND_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ ONDEMAND_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for ONDEMAND_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `ONDEMAND` writer - On Demand Control"]
+pub struct ONDEMAND_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ONDEMAND_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7);
+ self.w
+ }
+}
+#[doc = "Oscillator Start-Up Time\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum STARTUP_A {
+ #[doc = "0: 0.122 ms"]
+ CYCLE1 = 0,
+ #[doc = "1: 1.068 ms"]
+ CYCLE32 = 1,
+ #[doc = "2: 62.6 ms"]
+ CYCLE2048 = 2,
+ #[doc = "3: 125 ms"]
+ CYCLE4096 = 3,
+ #[doc = "4: 500 ms"]
+ CYCLE16384 = 4,
+ #[doc = "5: 1000 ms"]
+ CYCLE32768 = 5,
+ #[doc = "6: 2000 ms"]
+ CYCLE65536 = 6,
+ #[doc = "7: 4000 ms"]
+ CYCLE131072 = 7,
+}
+impl From<STARTUP_A> for u8 {
+ #[inline(always)]
+ fn from(variant: STARTUP_A) -> Self {
+ variant as _
+ }
+}
+#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"]
+pub struct STARTUP_R(crate::FieldReader<u8, STARTUP_A>);
+impl STARTUP_R {
+ pub(crate) fn new(bits: u8) -> Self {
+ STARTUP_R(crate::FieldReader::new(bits))
+ }
+ #[doc = r"Get enumerated values variant"]
+ #[inline(always)]
+ pub fn variant(&self) -> STARTUP_A {
+ match self.bits {
+ 0 => STARTUP_A::CYCLE1,
+ 1 => STARTUP_A::CYCLE32,
+ 2 => STARTUP_A::CYCLE2048,
+ 3 => STARTUP_A::CYCLE4096,
+ 4 => STARTUP_A::CYCLE16384,
+ 5 => STARTUP_A::CYCLE32768,
+ 6 => STARTUP_A::CYCLE65536,
+ 7 => STARTUP_A::CYCLE131072,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Checks if the value of the field is `CYCLE1`"]
+ #[inline(always)]
+ pub fn is_cycle1(&self) -> bool {
+ **self == STARTUP_A::CYCLE1
+ }
+ #[doc = "Checks if the value of the field is `CYCLE32`"]
+ #[inline(always)]
+ pub fn is_cycle32(&self) -> bool {
+ **self == STARTUP_A::CYCLE32
+ }
+ #[doc = "Checks if the value of the field is `CYCLE2048`"]
+ #[inline(always)]
+ pub fn is_cycle2048(&self) -> bool {
+ **self == STARTUP_A::CYCLE2048
+ }
+ #[doc = "Checks if the value of the field is `CYCLE4096`"]
+ #[inline(always)]
+ pub fn is_cycle4096(&self) -> bool {
+ **self == STARTUP_A::CYCLE4096
+ }
+ #[doc = "Checks if the value of the field is `CYCLE16384`"]
+ #[inline(always)]
+ pub fn is_cycle16384(&self) -> bool {
+ **self == STARTUP_A::CYCLE16384
+ }
+ #[doc = "Checks if the value of the field is `CYCLE32768`"]
+ #[inline(always)]
+ pub fn is_cycle32768(&self) -> bool {
+ **self == STARTUP_A::CYCLE32768
+ }
+ #[doc = "Checks if the value of the field is `CYCLE65536`"]
+ #[inline(always)]
+ pub fn is_cycle65536(&self) -> bool {
+ **self == STARTUP_A::CYCLE65536
+ }
+ #[doc = "Checks if the value of the field is `CYCLE131072`"]
+ #[inline(always)]
+ pub fn is_cycle131072(&self) -> bool {
+ **self == STARTUP_A::CYCLE131072
+ }
+}
+impl core::ops::Deref for STARTUP_R {
+ type Target = crate::FieldReader<u8, STARTUP_A>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"]
+pub struct STARTUP_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> STARTUP_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ pub fn variant(self, variant: STARTUP_A) -> &'a mut W {
+ self.bits(variant.into())
+ }
+ #[doc = "0.122 ms"]
+ #[inline(always)]
+ pub fn cycle1(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE1)
+ }
+ #[doc = "1.068 ms"]
+ #[inline(always)]
+ pub fn cycle32(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE32)
+ }
+ #[doc = "62.6 ms"]
+ #[inline(always)]
+ pub fn cycle2048(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE2048)
+ }
+ #[doc = "125 ms"]
+ #[inline(always)]
+ pub fn cycle4096(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE4096)
+ }
+ #[doc = "500 ms"]
+ #[inline(always)]
+ pub fn cycle16384(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE16384)
+ }
+ #[doc = "1000 ms"]
+ #[inline(always)]
+ pub fn cycle32768(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE32768)
+ }
+ #[doc = "2000 ms"]
+ #[inline(always)]
+ pub fn cycle65536(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE65536)
+ }
+ #[doc = "4000 ms"]
+ #[inline(always)]
+ pub fn cycle131072(self) -> &'a mut W {
+ self.variant(STARTUP_A::CYCLE131072)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x07 << 8)) | ((value as u16 & 0x07) << 8);
+ self.w
+ }
+}
+#[doc = "Field `WRTLOCK` reader - Write Lock"]
+pub struct WRTLOCK_R(crate::FieldReader<bool, bool>);
+impl WRTLOCK_R {
+ pub(crate) fn new(bits: bool) -> Self {
+ WRTLOCK_R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for WRTLOCK_R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `WRTLOCK` writer - Write Lock"]
+pub struct WRTLOCK_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> WRTLOCK_W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u16 & 0x01) << 12);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 1 - Oscillator Enable"]
+ #[inline(always)]
+ pub fn enable(&self) -> ENABLE_R {
+ ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - Crystal Oscillator Enable"]
+ #[inline(always)]
+ pub fn xtalen(&self) -> XTALEN_R {
+ XTALEN_R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+ #[doc = "Bit 3 - 32kHz Output Enable"]
+ #[inline(always)]
+ pub fn en32k(&self) -> EN32K_R {
+ EN32K_R::new(((self.bits >> 3) & 0x01) != 0)
+ }
+ #[doc = "Bit 4 - 1kHz Output Enable"]
+ #[inline(always)]
+ pub fn en1k(&self) -> EN1K_R {
+ EN1K_R::new(((self.bits >> 4) & 0x01) != 0)
+ }
+ #[doc = "Bit 6 - Run in Standby"]
+ #[inline(always)]
+ pub fn runstdby(&self) -> RUNSTDBY_R {
+ RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0)
+ }
+ #[doc = "Bit 7 - On Demand Control"]
+ #[inline(always)]
+ pub fn ondemand(&self) -> ONDEMAND_R {
+ ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0)
+ }
+ #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
+ #[inline(always)]
+ pub fn startup(&self) -> STARTUP_R {
+ STARTUP_R::new(((self.bits >> 8) & 0x07) as u8)
+ }
+ #[doc = "Bit 12 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&self) -> WRTLOCK_R {
+ WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 1 - Oscillator Enable"]
+ #[inline(always)]
+ pub fn enable(&mut self) -> ENABLE_W {
+ ENABLE_W { w: self }
+ }
+ #[doc = "Bit 2 - Crystal Oscillator Enable"]
+ #[inline(always)]
+ pub fn xtalen(&mut self) -> XTALEN_W {
+ XTALEN_W { w: self }
+ }
+ #[doc = "Bit 3 - 32kHz Output Enable"]
+ #[inline(always)]
+ pub fn en32k(&mut self) -> EN32K_W {
+ EN32K_W { w: self }
+ }
+ #[doc = "Bit 4 - 1kHz Output Enable"]
+ #[inline(always)]
+ pub fn en1k(&mut self) -> EN1K_W {
+ EN1K_W { w: self }
+ }
+ #[doc = "Bit 6 - Run in Standby"]
+ #[inline(always)]
+ pub fn runstdby(&mut self) -> RUNSTDBY_W {
+ RUNSTDBY_W { w: self }
+ }
+ #[doc = "Bit 7 - On Demand Control"]
+ #[inline(always)]
+ pub fn ondemand(&mut self) -> ONDEMAND_W {
+ ONDEMAND_W { w: self }
+ }
+ #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
+ #[inline(always)]
+ pub fn startup(&mut self) -> STARTUP_W {
+ STARTUP_W { w: self }
+ }
+ #[doc = "Bit 12 - Write Lock"]
+ #[inline(always)]
+ pub fn wrtlock(&mut self) -> WRTLOCK_W {
+ WRTLOCK_W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"]
+pub struct XOSC32K_SPEC;
+impl crate::RegisterSpec for XOSC32K_SPEC {
+ type Ux = u16;
+}
+#[doc = "`read()` method returns [xosc32k::R](R) reader structure"]
+impl crate::Readable for XOSC32K_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"]
+impl crate::Writable for XOSC32K_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets XOSC32K to value 0x80"]
+impl crate::Resettable for XOSC32K_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0x80
+ }
+}
generated by cgit v1.2.3-70-g09d2 (git 2.51.1) at 2025-12-06 06:48:47 +0000