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-rw-r--r--src/mclk/apbbmask.rs250
1 files changed, 250 insertions, 0 deletions
diff --git a/src/mclk/apbbmask.rs b/src/mclk/apbbmask.rs
new file mode 100644
index 0000000..aa7d9d0
--- /dev/null
+++ b/src/mclk/apbbmask.rs
@@ -0,0 +1,250 @@
+#[doc = "Register `APBBMASK` reader"]
+pub struct R(crate::R<APBBMASK_SPEC>);
+impl core::ops::Deref for R {
+ type Target = crate::R<APBBMASK_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl From<crate::R<APBBMASK_SPEC>> for R {
+ #[inline(always)]
+ fn from(reader: crate::R<APBBMASK_SPEC>) -> Self {
+ R(reader)
+ }
+}
+#[doc = "Register `APBBMASK` writer"]
+pub struct W(crate::W<APBBMASK_SPEC>);
+impl core::ops::Deref for W {
+ type Target = crate::W<APBBMASK_SPEC>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+impl core::ops::DerefMut for W {
+ #[inline(always)]
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.0
+ }
+}
+impl From<crate::W<APBBMASK_SPEC>> for W {
+ #[inline(always)]
+ fn from(writer: crate::W<APBBMASK_SPEC>) -> Self {
+ W(writer)
+ }
+}
+#[doc = "Field `PORT_` reader - PORT APB Clock Enable"]
+pub struct PORT__R(crate::FieldReader<bool, bool>);
+impl PORT__R {
+ pub(crate) fn new(bits: bool) -> Self {
+ PORT__R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for PORT__R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `PORT_` writer - PORT APB Clock Enable"]
+pub struct PORT__W<'a> {
+ w: &'a mut W,
+}
+impl<'a> PORT__W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+ self.w
+ }
+}
+#[doc = "Field `DSU_` reader - DSU APB Clock Enable"]
+pub struct DSU__R(crate::FieldReader<bool, bool>);
+impl DSU__R {
+ pub(crate) fn new(bits: bool) -> Self {
+ DSU__R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for DSU__R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `DSU_` writer - DSU APB Clock Enable"]
+pub struct DSU__W<'a> {
+ w: &'a mut W,
+}
+impl<'a> DSU__W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+ self.w
+ }
+}
+#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"]
+pub struct NVMCTRL__R(crate::FieldReader<bool, bool>);
+impl NVMCTRL__R {
+ pub(crate) fn new(bits: bool) -> Self {
+ NVMCTRL__R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for NVMCTRL__R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"]
+pub struct NVMCTRL__W<'a> {
+ w: &'a mut W,
+}
+impl<'a> NVMCTRL__W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
+ self.w
+ }
+}
+#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"]
+pub struct HMATRIXHS__R(crate::FieldReader<bool, bool>);
+impl HMATRIXHS__R {
+ pub(crate) fn new(bits: bool) -> Self {
+ HMATRIXHS__R(crate::FieldReader::new(bits))
+ }
+}
+impl core::ops::Deref for HMATRIXHS__R {
+ type Target = crate::FieldReader<bool, bool>;
+ #[inline(always)]
+ fn deref(&self) -> &Self::Target {
+ &self.0
+ }
+}
+#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"]
+pub struct HMATRIXHS__W<'a> {
+ w: &'a mut W,
+}
+impl<'a> HMATRIXHS__W<'a> {
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+ self.w
+ }
+}
+impl R {
+ #[doc = "Bit 0 - PORT APB Clock Enable"]
+ #[inline(always)]
+ pub fn port_(&self) -> PORT__R {
+ PORT__R::new((self.bits & 0x01) != 0)
+ }
+ #[doc = "Bit 1 - DSU APB Clock Enable"]
+ #[inline(always)]
+ pub fn dsu_(&self) -> DSU__R {
+ DSU__R::new(((self.bits >> 1) & 0x01) != 0)
+ }
+ #[doc = "Bit 2 - NVMCTRL APB Clock Enable"]
+ #[inline(always)]
+ pub fn nvmctrl_(&self) -> NVMCTRL__R {
+ NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0)
+ }
+ #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"]
+ #[inline(always)]
+ pub fn hmatrixhs_(&self) -> HMATRIXHS__R {
+ HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - PORT APB Clock Enable"]
+ #[inline(always)]
+ pub fn port_(&mut self) -> PORT__W {
+ PORT__W { w: self }
+ }
+ #[doc = "Bit 1 - DSU APB Clock Enable"]
+ #[inline(always)]
+ pub fn dsu_(&mut self) -> DSU__W {
+ DSU__W { w: self }
+ }
+ #[doc = "Bit 2 - NVMCTRL APB Clock Enable"]
+ #[inline(always)]
+ pub fn nvmctrl_(&mut self) -> NVMCTRL__W {
+ NVMCTRL__W { w: self }
+ }
+ #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"]
+ #[inline(always)]
+ pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W {
+ HMATRIXHS__W { w: self }
+ }
+ #[doc = "Writes raw bits to the register."]
+ #[inline(always)]
+ pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+ self.0.bits(bits);
+ self
+ }
+}
+#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"]
+pub struct APBBMASK_SPEC;
+impl crate::RegisterSpec for APBBMASK_SPEC {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [apbbmask::R](R) reader structure"]
+impl crate::Readable for APBBMASK_SPEC {
+ type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"]
+impl crate::Writable for APBBMASK_SPEC {
+ type Writer = W;
+}
+#[doc = "`reset()` method sets APBBMASK to value 0x07"]
+impl crate::Resettable for APBBMASK_SPEC {
+ #[inline(always)]
+ fn reset_value() -> Self::Ux {
+ 0x07
+ }
+}
generated by cgit v1.2.3-70-g09d2 (git 2.51.1) at 2025-12-06 06:35:33 +0000