diff options
Diffstat (limited to 'src/mclk')
| -rw-r--r-- | src/mclk/ahbmask.rs | 710 | ||||
| -rw-r--r-- | src/mclk/apbamask.rs | 664 | ||||
| -rw-r--r-- | src/mclk/apbbmask.rs | 250 | ||||
| -rw-r--r-- | src/mclk/apbcmask.rs | 1078 | ||||
| -rw-r--r-- | src/mclk/apbdmask.rs | 296 | ||||
| -rw-r--r-- | src/mclk/cpudiv.rs | 229 | ||||
| -rw-r--r-- | src/mclk/intenclr.rs | 112 | ||||
| -rw-r--r-- | src/mclk/intenset.rs | 112 | ||||
| -rw-r--r-- | src/mclk/intflag.rs | 112 |
9 files changed, 3563 insertions, 0 deletions
diff --git a/src/mclk/ahbmask.rs b/src/mclk/ahbmask.rs new file mode 100644 index 0000000..9649872 --- /dev/null +++ b/src/mclk/ahbmask.rs @@ -0,0 +1,710 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R<AHBMASK_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<AHBMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<AHBMASK_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<AHBMASK_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W<AHBMASK_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<AHBMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<AHBMASK_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<AHBMASK_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub struct HPB0__R(crate::FieldReader<bool, bool>); +impl HPB0__R { + pub(crate) fn new(bits: bool) -> Self { + HPB0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub struct HPB0__W<'a> { + w: &'a mut W, +} +impl<'a> HPB0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub struct HPB1__R(crate::FieldReader<bool, bool>); +impl HPB1__R { + pub(crate) fn new(bits: bool) -> Self { + HPB1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub struct HPB1__W<'a> { + w: &'a mut W, +} +impl<'a> HPB1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub struct HPB2__R(crate::FieldReader<bool, bool>); +impl HPB2__R { + pub(crate) fn new(bits: bool) -> Self { + HPB2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB2__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub struct HPB2__W<'a> { + w: &'a mut W, +} +impl<'a> HPB2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub struct DSU__R(crate::FieldReader<bool, bool>); +impl DSU__R { + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__R(crate::FieldReader<bool, bool>); +impl HMATRIXHS__R { + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS AHB Clock Mask"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__R(crate::FieldReader<bool, bool>); +impl NVMCTRL__R { + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub struct HSRAM__R(crate::FieldReader<bool, bool>); +impl HSRAM__R { + pub(crate) fn new(bits: bool) -> Self { + HSRAM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HSRAM__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub struct HSRAM__W<'a> { + w: &'a mut W, +} +impl<'a> HSRAM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub struct DMAC__R(crate::FieldReader<bool, bool>); +impl DMAC__R { + pub(crate) fn new(bits: bool) -> Self { + DMAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DMAC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub struct DMAC__W<'a> { + w: &'a mut W, +} +impl<'a> DMAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `CAN0_` reader - CAN0 AHB Clock Mask"] +pub struct CAN0__R(crate::FieldReader<bool, bool>); +impl CAN0__R { + pub(crate) fn new(bits: bool) -> Self { + CAN0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN0_` writer - CAN0 AHB Clock Mask"] +pub struct CAN0__W<'a> { + w: &'a mut W, +} +impl<'a> CAN0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `CAN1_` reader - CAN1 AHB Clock Mask"] +pub struct CAN1__R(crate::FieldReader<bool, bool>); +impl CAN1__R { + pub(crate) fn new(bits: bool) -> Self { + CAN1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CAN1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CAN1_` writer - CAN1 AHB Clock Mask"] +pub struct CAN1__W<'a> { + w: &'a mut W, +} +impl<'a> CAN1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub struct PAC__R(crate::FieldReader<bool, bool>); +impl PAC__R { + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__R(crate::FieldReader<bool, bool>); +impl NVMCTRL_PICACHU__R { + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL_PICACHU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL_PICACHU__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub struct NVMCTRL_PICACHU__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL_PICACHU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `DIVAS_` reader - DIVAS AHB Clock Mask"] +pub struct DIVAS__R(crate::FieldReader<bool, bool>); +impl DIVAS__R { + pub(crate) fn new(bits: bool) -> Self { + DIVAS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DIVAS__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DIVAS_` writer - DIVAS AHB Clock Mask"] +pub struct DIVAS__W<'a> { + w: &'a mut W, +} +impl<'a> DIVAS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `HPB3_` reader - HPB3 AHB Clock Mask"] +pub struct HPB3__R(crate::FieldReader<bool, bool>); +impl HPB3__R { + pub(crate) fn new(bits: bool) -> Self { + HPB3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HPB3__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HPB3_` writer - HPB3 AHB Clock Mask"] +pub struct HPB3__W<'a> { + w: &'a mut W, +} +impl<'a> HPB3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&self) -> CAN0__R { + CAN0__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&self) -> CAN1__R { + CAN1__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&self) -> DIVAS__R { + DIVAS__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&self) -> HPB3__R { + HPB3__R::new(((self.bits >> 13) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&mut self) -> HPB0__W { + HPB0__W { w: self } + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&mut self) -> HPB1__W { + HPB1__W { w: self } + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&mut self) -> HPB2__W { + HPB2__W { w: self } + } + #[doc = "Bit 3 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 4 - HMATRIXHS AHB Clock Mask"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Bit 5 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 6 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&mut self) -> HSRAM__W { + HSRAM__W { w: self } + } + #[doc = "Bit 7 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&mut self) -> DMAC__W { + DMAC__W { w: self } + } + #[doc = "Bit 8 - CAN0 AHB Clock Mask"] + #[inline(always)] + pub fn can0_(&mut self) -> CAN0__W { + CAN0__W { w: self } + } + #[doc = "Bit 9 - CAN1 AHB Clock Mask"] + #[inline(always)] + pub fn can1_(&mut self) -> CAN1__W { + CAN1__W { w: self } + } + #[doc = "Bit 10 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 11 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W { + NVMCTRL_PICACHU__W { w: self } + } + #[doc = "Bit 12 - DIVAS AHB Clock Mask"] + #[inline(always)] + pub fn divas_(&mut self) -> DIVAS__W { + DIVAS__W { w: self } + } + #[doc = "Bit 13 - HPB3 AHB Clock Mask"] + #[inline(always)] + pub fn hpb3_(&mut self) -> HPB3__W { + HPB3__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets AHBMASK to value 0x3cff"] +impl crate::Resettable for AHBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x3cff + } +} diff --git a/src/mclk/apbamask.rs b/src/mclk/apbamask.rs new file mode 100644 index 0000000..9c3ee9f --- /dev/null +++ b/src/mclk/apbamask.rs @@ -0,0 +1,664 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R<APBAMASK_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<APBAMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<APBAMASK_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<APBAMASK_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W<APBAMASK_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<APBAMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<APBAMASK_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<APBAMASK_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub struct PAC__R(crate::FieldReader<bool, bool>); +impl PAC__R { + pub(crate) fn new(bits: bool) -> Self { + PAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PAC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub struct PAC__W<'a> { + w: &'a mut W, +} +impl<'a> PAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub struct PM__R(crate::FieldReader<bool, bool>); +impl PM__R { + pub(crate) fn new(bits: bool) -> Self { + PM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PM__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub struct PM__W<'a> { + w: &'a mut W, +} +impl<'a> PM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub struct MCLK__R(crate::FieldReader<bool, bool>); +impl MCLK__R { + pub(crate) fn new(bits: bool) -> Self { + MCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for MCLK__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub struct MCLK__W<'a> { + w: &'a mut W, +} +impl<'a> MCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub struct RSTC__R(crate::FieldReader<bool, bool>); +impl RSTC__R { + pub(crate) fn new(bits: bool) -> Self { + RSTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RSTC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub struct RSTC__W<'a> { + w: &'a mut W, +} +impl<'a> RSTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__R(crate::FieldReader<bool, bool>); +impl OSCCTRL__R { + pub(crate) fn new(bits: bool) -> Self { + OSCCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSCCTRL__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub struct OSCCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSCCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__R(crate::FieldReader<bool, bool>); +impl OSC32KCTRL__R { + pub(crate) fn new(bits: bool) -> Self { + OSC32KCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for OSC32KCTRL__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub struct OSC32KCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> OSC32KCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub struct SUPC__R(crate::FieldReader<bool, bool>); +impl SUPC__R { + pub(crate) fn new(bits: bool) -> Self { + SUPC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SUPC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub struct SUPC__W<'a> { + w: &'a mut W, +} +impl<'a> SUPC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub struct GCLK__R(crate::FieldReader<bool, bool>); +impl GCLK__R { + pub(crate) fn new(bits: bool) -> Self { + GCLK__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for GCLK__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub struct GCLK__W<'a> { + w: &'a mut W, +} +impl<'a> GCLK__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7); + self.w + } +} +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub struct WDT__R(crate::FieldReader<bool, bool>); +impl WDT__R { + pub(crate) fn new(bits: bool) -> Self { + WDT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for WDT__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub struct WDT__W<'a> { + w: &'a mut W, +} +impl<'a> WDT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8); + self.w + } +} +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub struct RTC__R(crate::FieldReader<bool, bool>); +impl RTC__R { + pub(crate) fn new(bits: bool) -> Self { + RTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for RTC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub struct RTC__W<'a> { + w: &'a mut W, +} +impl<'a> RTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub struct EIC__R(crate::FieldReader<bool, bool>); +impl EIC__R { + pub(crate) fn new(bits: bool) -> Self { + EIC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EIC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub struct EIC__W<'a> { + w: &'a mut W, +} +impl<'a> EIC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub struct FREQM__R(crate::FieldReader<bool, bool>); +impl FREQM__R { + pub(crate) fn new(bits: bool) -> Self { + FREQM__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for FREQM__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub struct FREQM__W<'a> { + w: &'a mut W, +} +impl<'a> FREQM__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TSENS_` reader - TSENS APB Clock Enable"] +pub struct TSENS__R(crate::FieldReader<bool, bool>); +impl TSENS__R { + pub(crate) fn new(bits: bool) -> Self { + TSENS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TSENS__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TSENS_` writer - TSENS APB Clock Enable"] +pub struct TSENS__W<'a> { + w: &'a mut W, +} +impl<'a> TSENS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 0x01) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 0x01) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&self) -> TSENS__R { + TSENS__R::new(((self.bits >> 12) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&mut self) -> PAC__W { + PAC__W { w: self } + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&mut self) -> PM__W { + PM__W { w: self } + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&mut self) -> MCLK__W { + MCLK__W { w: self } + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&mut self) -> RSTC__W { + RSTC__W { w: self } + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&mut self) -> OSCCTRL__W { + OSCCTRL__W { w: self } + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W { + OSC32KCTRL__W { w: self } + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&mut self) -> SUPC__W { + SUPC__W { w: self } + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&mut self) -> GCLK__W { + GCLK__W { w: self } + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&mut self) -> WDT__W { + WDT__W { w: self } + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&mut self) -> RTC__W { + RTC__W { w: self } + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&mut self) -> EIC__W { + EIC__W { w: self } + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&mut self) -> FREQM__W { + FREQM__W { w: self } + } + #[doc = "Bit 12 - TSENS APB Clock Enable"] + #[inline(always)] + pub fn tsens_(&mut self) -> TSENS__W { + TSENS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBAMASK to value 0x0fff"] +impl crate::Resettable for APBAMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x0fff + } +} diff --git a/src/mclk/apbbmask.rs b/src/mclk/apbbmask.rs new file mode 100644 index 0000000..aa7d9d0 --- /dev/null +++ b/src/mclk/apbbmask.rs @@ -0,0 +1,250 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R<APBBMASK_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<APBBMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<APBBMASK_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<APBBMASK_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W<APBBMASK_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<APBBMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<APBBMASK_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<APBBMASK_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub struct PORT__R(crate::FieldReader<bool, bool>); +impl PORT__R { + pub(crate) fn new(bits: bool) -> Self { + PORT__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PORT__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub struct PORT__W<'a> { + w: &'a mut W, +} +impl<'a> PORT__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub struct DSU__R(crate::FieldReader<bool, bool>); +impl DSU__R { + pub(crate) fn new(bits: bool) -> Self { + DSU__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DSU__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub struct DSU__W<'a> { + w: &'a mut W, +} +impl<'a> DSU__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__R(crate::FieldReader<bool, bool>); +impl NVMCTRL__R { + pub(crate) fn new(bits: bool) -> Self { + NVMCTRL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for NVMCTRL__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub struct NVMCTRL__W<'a> { + w: &'a mut W, +} +impl<'a> NVMCTRL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `HMATRIXHS_` reader - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__R(crate::FieldReader<bool, bool>); +impl HMATRIXHS__R { + pub(crate) fn new(bits: bool) -> Self { + HMATRIXHS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for HMATRIXHS__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `HMATRIXHS_` writer - HMATRIXHS APB Clock Enable"] +pub struct HMATRIXHS__W<'a> { + w: &'a mut W, +} +impl<'a> HMATRIXHS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +impl R { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&self) -> HMATRIXHS__R { + HMATRIXHS__R::new(((self.bits >> 5) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&mut self) -> PORT__W { + PORT__W { w: self } + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&mut self) -> DSU__W { + DSU__W { w: self } + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W { + NVMCTRL__W { w: self } + } + #[doc = "Bit 5 - HMATRIXHS APB Clock Enable"] + #[inline(always)] + pub fn hmatrixhs_(&mut self) -> HMATRIXHS__W { + HMATRIXHS__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBBMASK to value 0x07"] +impl crate::Resettable for APBBMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x07 + } +} diff --git a/src/mclk/apbcmask.rs b/src/mclk/apbcmask.rs new file mode 100644 index 0000000..ccc29e5 --- /dev/null +++ b/src/mclk/apbcmask.rs @@ -0,0 +1,1078 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R<APBCMASK_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<APBCMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<APBCMASK_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<APBCMASK_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W<APBCMASK_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<APBCMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<APBCMASK_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<APBCMASK_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub struct EVSYS__R(crate::FieldReader<bool, bool>); +impl EVSYS__R { + pub(crate) fn new(bits: bool) -> Self { + EVSYS__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for EVSYS__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub struct EVSYS__W<'a> { + w: &'a mut W, +} +impl<'a> EVSYS__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__R(crate::FieldReader<bool, bool>); +impl SERCOM0__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub struct SERCOM0__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__R(crate::FieldReader<bool, bool>); +impl SERCOM1__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub struct SERCOM1__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__R(crate::FieldReader<bool, bool>); +impl SERCOM2__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM2__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub struct SERCOM2__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__R(crate::FieldReader<bool, bool>); +impl SERCOM3__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM3__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub struct SERCOM3__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +#[doc = "Field `SERCOM4_` reader - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__R(crate::FieldReader<bool, bool>); +impl SERCOM4__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM4__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM4_` writer - SERCOM4 APB Clock Enable"] +pub struct SERCOM4__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5); + self.w + } +} +#[doc = "Field `SERCOM5_` reader - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__R(crate::FieldReader<bool, bool>); +impl SERCOM5__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM5__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM5_` writer - SERCOM5 APB Clock Enable"] +pub struct SERCOM5__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6); + self.w + } +} +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub struct TCC0__R(crate::FieldReader<bool, bool>); +impl TCC0__R { + pub(crate) fn new(bits: bool) -> Self { + TCC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub struct TCC0__W<'a> { + w: &'a mut W, +} +impl<'a> TCC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9); + self.w + } +} +#[doc = "Field `TCC1_` reader - TCC1 APB Clock Enable"] +pub struct TCC1__R(crate::FieldReader<bool, bool>); +impl TCC1__R { + pub(crate) fn new(bits: bool) -> Self { + TCC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC1_` writer - TCC1 APB Clock Enable"] +pub struct TCC1__W<'a> { + w: &'a mut W, +} +impl<'a> TCC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10); + self.w + } +} +#[doc = "Field `TCC2_` reader - TCC2 APB Clock Enable"] +pub struct TCC2__R(crate::FieldReader<bool, bool>); +impl TCC2__R { + pub(crate) fn new(bits: bool) -> Self { + TCC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TCC2__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TCC2_` writer - TCC2 APB Clock Enable"] +pub struct TCC2__W<'a> { + w: &'a mut W, +} +impl<'a> TCC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11); + self.w + } +} +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub struct TC0__R(crate::FieldReader<bool, bool>); +impl TC0__R { + pub(crate) fn new(bits: bool) -> Self { + TC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub struct TC0__W<'a> { + w: &'a mut W, +} +impl<'a> TC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12); + self.w + } +} +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub struct TC1__R(crate::FieldReader<bool, bool>); +impl TC1__R { + pub(crate) fn new(bits: bool) -> Self { + TC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub struct TC1__W<'a> { + w: &'a mut W, +} +impl<'a> TC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13); + self.w + } +} +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub struct TC2__R(crate::FieldReader<bool, bool>); +impl TC2__R { + pub(crate) fn new(bits: bool) -> Self { + TC2__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC2__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub struct TC2__W<'a> { + w: &'a mut W, +} +impl<'a> TC2__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14); + self.w + } +} +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub struct TC3__R(crate::FieldReader<bool, bool>); +impl TC3__R { + pub(crate) fn new(bits: bool) -> Self { + TC3__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC3__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub struct TC3__W<'a> { + w: &'a mut W, +} +impl<'a> TC3__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15); + self.w + } +} +#[doc = "Field `TC4_` reader - TC4 APB Clock Enable"] +pub struct TC4__R(crate::FieldReader<bool, bool>); +impl TC4__R { + pub(crate) fn new(bits: bool) -> Self { + TC4__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC4__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC4_` writer - TC4 APB Clock Enable"] +pub struct TC4__W<'a> { + w: &'a mut W, +} +impl<'a> TC4__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16); + self.w + } +} +#[doc = "Field `ADC0_` reader - ADC0 APB Clock Enable"] +pub struct ADC0__R(crate::FieldReader<bool, bool>); +impl ADC0__R { + pub(crate) fn new(bits: bool) -> Self { + ADC0__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC0__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC0_` writer - ADC0 APB Clock Enable"] +pub struct ADC0__W<'a> { + w: &'a mut W, +} +impl<'a> ADC0__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17); + self.w + } +} +#[doc = "Field `ADC1_` reader - ADC1 APB Clock Enable"] +pub struct ADC1__R(crate::FieldReader<bool, bool>); +impl ADC1__R { + pub(crate) fn new(bits: bool) -> Self { + ADC1__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for ADC1__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `ADC1_` writer - ADC1 APB Clock Enable"] +pub struct ADC1__W<'a> { + w: &'a mut W, +} +impl<'a> ADC1__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18); + self.w + } +} +#[doc = "Field `SDADC_` reader - SDADC APB Clock Enable"] +pub struct SDADC__R(crate::FieldReader<bool, bool>); +impl SDADC__R { + pub(crate) fn new(bits: bool) -> Self { + SDADC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SDADC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SDADC_` writer - SDADC APB Clock Enable"] +pub struct SDADC__W<'a> { + w: &'a mut W, +} +impl<'a> SDADC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19); + self.w + } +} +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub struct AC__R(crate::FieldReader<bool, bool>); +impl AC__R { + pub(crate) fn new(bits: bool) -> Self { + AC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for AC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub struct AC__W<'a> { + w: &'a mut W, +} +impl<'a> AC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20); + self.w + } +} +#[doc = "Field `DAC_` reader - DAC APB Clock Enable"] +pub struct DAC__R(crate::FieldReader<bool, bool>); +impl DAC__R { + pub(crate) fn new(bits: bool) -> Self { + DAC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for DAC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `DAC_` writer - DAC APB Clock Enable"] +pub struct DAC__W<'a> { + w: &'a mut W, +} +impl<'a> DAC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21); + self.w + } +} +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub struct PTC__R(crate::FieldReader<bool, bool>); +impl PTC__R { + pub(crate) fn new(bits: bool) -> Self { + PTC__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for PTC__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub struct PTC__W<'a> { + w: &'a mut W, +} +impl<'a> PTC__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22); + self.w + } +} +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub struct CCL__R(crate::FieldReader<bool, bool>); +impl CCL__R { + pub(crate) fn new(bits: bool) -> Self { + CCL__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CCL__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub struct CCL__W<'a> { + w: &'a mut W, +} +impl<'a> CCL__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23); + self.w + } +} +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 0x01) != 0) + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&self) -> SERCOM4__R { + SERCOM4__R::new(((self.bits >> 5) & 0x01) != 0) + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&self) -> SERCOM5__R { + SERCOM5__R::new(((self.bits >> 6) & 0x01) != 0) + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 9) & 0x01) != 0) + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&self) -> TCC1__R { + TCC1__R::new(((self.bits >> 10) & 0x01) != 0) + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&self) -> TCC2__R { + TCC2__R::new(((self.bits >> 11) & 0x01) != 0) + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 12) & 0x01) != 0) + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 13) & 0x01) != 0) + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 14) & 0x01) != 0) + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 15) & 0x01) != 0) + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&self) -> TC4__R { + TC4__R::new(((self.bits >> 16) & 0x01) != 0) + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&self) -> ADC0__R { + ADC0__R::new(((self.bits >> 17) & 0x01) != 0) + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&self) -> ADC1__R { + ADC1__R::new(((self.bits >> 18) & 0x01) != 0) + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&self) -> SDADC__R { + SDADC__R::new(((self.bits >> 19) & 0x01) != 0) + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 20) & 0x01) != 0) + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&self) -> DAC__R { + DAC__R::new(((self.bits >> 21) & 0x01) != 0) + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 22) & 0x01) != 0) + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 23) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&mut self) -> EVSYS__W { + EVSYS__W { w: self } + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&mut self) -> SERCOM0__W { + SERCOM0__W { w: self } + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&mut self) -> SERCOM1__W { + SERCOM1__W { w: self } + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&mut self) -> SERCOM2__W { + SERCOM2__W { w: self } + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&mut self) -> SERCOM3__W { + SERCOM3__W { w: self } + } + #[doc = "Bit 5 - SERCOM4 APB Clock Enable"] + #[inline(always)] + pub fn sercom4_(&mut self) -> SERCOM4__W { + SERCOM4__W { w: self } + } + #[doc = "Bit 6 - SERCOM5 APB Clock Enable"] + #[inline(always)] + pub fn sercom5_(&mut self) -> SERCOM5__W { + SERCOM5__W { w: self } + } + #[doc = "Bit 9 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&mut self) -> TCC0__W { + TCC0__W { w: self } + } + #[doc = "Bit 10 - TCC1 APB Clock Enable"] + #[inline(always)] + pub fn tcc1_(&mut self) -> TCC1__W { + TCC1__W { w: self } + } + #[doc = "Bit 11 - TCC2 APB Clock Enable"] + #[inline(always)] + pub fn tcc2_(&mut self) -> TCC2__W { + TCC2__W { w: self } + } + #[doc = "Bit 12 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&mut self) -> TC0__W { + TC0__W { w: self } + } + #[doc = "Bit 13 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&mut self) -> TC1__W { + TC1__W { w: self } + } + #[doc = "Bit 14 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&mut self) -> TC2__W { + TC2__W { w: self } + } + #[doc = "Bit 15 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&mut self) -> TC3__W { + TC3__W { w: self } + } + #[doc = "Bit 16 - TC4 APB Clock Enable"] + #[inline(always)] + pub fn tc4_(&mut self) -> TC4__W { + TC4__W { w: self } + } + #[doc = "Bit 17 - ADC0 APB Clock Enable"] + #[inline(always)] + pub fn adc0_(&mut self) -> ADC0__W { + ADC0__W { w: self } + } + #[doc = "Bit 18 - ADC1 APB Clock Enable"] + #[inline(always)] + pub fn adc1_(&mut self) -> ADC1__W { + ADC1__W { w: self } + } + #[doc = "Bit 19 - SDADC APB Clock Enable"] + #[inline(always)] + pub fn sdadc_(&mut self) -> SDADC__W { + SDADC__W { w: self } + } + #[doc = "Bit 20 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&mut self) -> AC__W { + AC__W { w: self } + } + #[doc = "Bit 21 - DAC APB Clock Enable"] + #[inline(always)] + pub fn dac_(&mut self) -> DAC__W { + DAC__W { w: self } + } + #[doc = "Bit 22 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&mut self) -> PTC__W { + PTC__W { w: self } + } + #[doc = "Bit 23 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&mut self) -> CCL__W { + CCL__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBCMASK to value 0"] +impl crate::Resettable for APBCMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/mclk/apbdmask.rs b/src/mclk/apbdmask.rs new file mode 100644 index 0000000..075b448 --- /dev/null +++ b/src/mclk/apbdmask.rs @@ -0,0 +1,296 @@ +#[doc = "Register `APBDMASK` reader"] +pub struct R(crate::R<APBDMASK_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<APBDMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<APBDMASK_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<APBDMASK_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `APBDMASK` writer"] +pub struct W(crate::W<APBDMASK_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<APBDMASK_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<APBDMASK_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<APBDMASK_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `SERCOM6_` reader - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__R(crate::FieldReader<bool, bool>); +impl SERCOM6__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM6__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM6_` writer - SERCOM6 APB Clock Enable"] +pub struct SERCOM6__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); + self.w + } +} +#[doc = "Field `SERCOM7_` reader - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__R(crate::FieldReader<bool, bool>); +impl SERCOM7__R { + pub(crate) fn new(bits: bool) -> Self { + SERCOM7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for SERCOM7__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `SERCOM7_` writer - SERCOM7 APB Clock Enable"] +pub struct SERCOM7__W<'a> { + w: &'a mut W, +} +impl<'a> SERCOM7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); + self.w + } +} +#[doc = "Field `TC5_` reader - TC5 APB Clock Enable"] +pub struct TC5__R(crate::FieldReader<bool, bool>); +impl TC5__R { + pub(crate) fn new(bits: bool) -> Self { + TC5__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC5__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC5_` writer - TC5 APB Clock Enable"] +pub struct TC5__W<'a> { + w: &'a mut W, +} +impl<'a> TC5__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); + self.w + } +} +#[doc = "Field `TC6_` reader - TC6 APB Clock Enable"] +pub struct TC6__R(crate::FieldReader<bool, bool>); +impl TC6__R { + pub(crate) fn new(bits: bool) -> Self { + TC6__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC6__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC6_` writer - TC6 APB Clock Enable"] +pub struct TC6__W<'a> { + w: &'a mut W, +} +impl<'a> TC6__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); + self.w + } +} +#[doc = "Field `TC7_` reader - TC7 APB Clock Enable"] +pub struct TC7__R(crate::FieldReader<bool, bool>); +impl TC7__R { + pub(crate) fn new(bits: bool) -> Self { + TC7__R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for TC7__R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `TC7_` writer - TC7 APB Clock Enable"] +pub struct TC7__W<'a> { + w: &'a mut W, +} +impl<'a> TC7__W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4); + self.w + } +} +impl R { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&self) -> SERCOM6__R { + SERCOM6__R::new((self.bits & 0x01) != 0) + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&self) -> SERCOM7__R { + SERCOM7__R::new(((self.bits >> 1) & 0x01) != 0) + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&self) -> TC5__R { + TC5__R::new(((self.bits >> 2) & 0x01) != 0) + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&self) -> TC6__R { + TC6__R::new(((self.bits >> 3) & 0x01) != 0) + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&self) -> TC7__R { + TC7__R::new(((self.bits >> 4) & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - SERCOM6 APB Clock Enable"] + #[inline(always)] + pub fn sercom6_(&mut self) -> SERCOM6__W { + SERCOM6__W { w: self } + } + #[doc = "Bit 1 - SERCOM7 APB Clock Enable"] + #[inline(always)] + pub fn sercom7_(&mut self) -> SERCOM7__W { + SERCOM7__W { w: self } + } + #[doc = "Bit 2 - TC5 APB Clock Enable"] + #[inline(always)] + pub fn tc5_(&mut self) -> TC5__W { + TC5__W { w: self } + } + #[doc = "Bit 3 - TC6 APB Clock Enable"] + #[inline(always)] + pub fn tc6_(&mut self) -> TC6__W { + TC6__W { w: self } + } + #[doc = "Bit 4 - TC7 APB Clock Enable"] + #[inline(always)] + pub fn tc7_(&mut self) -> TC7__W { + TC7__W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBD Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbdmask](index.html) module"] +pub struct APBDMASK_SPEC; +impl crate::RegisterSpec for APBDMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbdmask::R](R) reader structure"] +impl crate::Readable for APBDMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbdmask::W](W) writer structure"] +impl crate::Writable for APBDMASK_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets APBDMASK to value 0"] +impl crate::Resettable for APBDMASK_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/mclk/cpudiv.rs b/src/mclk/cpudiv.rs new file mode 100644 index 0000000..3de945f --- /dev/null +++ b/src/mclk/cpudiv.rs @@ -0,0 +1,229 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R<CPUDIV_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<CPUDIV_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<CPUDIV_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<CPUDIV_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W<CPUDIV_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<CPUDIV_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<CPUDIV_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<CPUDIV_SPEC>) -> Self { + W(writer) + } +} +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq)] +#[repr(u8)] +pub enum CPUDIV_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From<CPUDIV_A> for u8 { + #[inline(always)] + fn from(variant: CPUDIV_A) -> Self { + variant as _ + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub struct CPUDIV_R(crate::FieldReader<u8, CPUDIV_A>); +impl CPUDIV_R { + pub(crate) fn new(bits: u8) -> Self { + CPUDIV_R(crate::FieldReader::new(bits)) + } + #[doc = r"Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option<CPUDIV_A> { + match self.bits { + 1 => Some(CPUDIV_A::DIV1), + 2 => Some(CPUDIV_A::DIV2), + 4 => Some(CPUDIV_A::DIV4), + 8 => Some(CPUDIV_A::DIV8), + 16 => Some(CPUDIV_A::DIV16), + 32 => Some(CPUDIV_A::DIV32), + 64 => Some(CPUDIV_A::DIV64), + 128 => Some(CPUDIV_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + **self == CPUDIV_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + **self == CPUDIV_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + **self == CPUDIV_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + **self == CPUDIV_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + **self == CPUDIV_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + **self == CPUDIV_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + **self == CPUDIV_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + **self == CPUDIV_A::DIV128 + } +} +impl core::ops::Deref for CPUDIV_R { + type Target = crate::FieldReader<u8, CPUDIV_A>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub struct CPUDIV_W<'a> { + w: &'a mut W, +} +impl<'a> CPUDIV_W<'a> { + #[doc = r"Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: CPUDIV_A) -> &'a mut W { + unsafe { self.bits(variant.into()) } + } + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIV_A::DIV128) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub unsafe fn bits(self, value: u8) -> &'a mut W { + self.w.bits = (self.w.bits & !0xff) | (value as u8 & 0xff); + self.w + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&mut self) -> CPUDIV_W { + CPUDIV_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} diff --git a/src/mclk/intenclr.rs b/src/mclk/intenclr.rs new file mode 100644 index 0000000..12f5b0f --- /dev/null +++ b/src/mclk/intenclr.rs @@ -0,0 +1,112 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R<INTENCLR_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENCLR_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENCLR_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W<INTENCLR_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENCLR_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENCLR_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENCLR_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader<bool, bool>); +impl CKRDY_R { + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/mclk/intenset.rs b/src/mclk/intenset.rs new file mode 100644 index 0000000..71cc927 --- /dev/null +++ b/src/mclk/intenset.rs @@ -0,0 +1,112 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R<INTENSET_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTENSET_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTENSET_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W<INTENSET_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTENSET_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTENSET_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTENSET_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub struct CKRDY_R(crate::FieldReader<bool, bool>); +impl CKRDY_R { + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0 + } +} diff --git a/src/mclk/intflag.rs b/src/mclk/intflag.rs new file mode 100644 index 0000000..269855e --- /dev/null +++ b/src/mclk/intflag.rs @@ -0,0 +1,112 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R<INTFLAG_SPEC>); +impl core::ops::Deref for R { + type Target = crate::R<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From<crate::R<INTFLAG_SPEC>> for R { + #[inline(always)] + fn from(reader: crate::R<INTFLAG_SPEC>) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W<INTFLAG_SPEC>); +impl core::ops::Deref for W { + type Target = crate::W<INTFLAG_SPEC>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From<crate::W<INTFLAG_SPEC>> for W { + #[inline(always)] + fn from(writer: crate::W<INTFLAG_SPEC>) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub struct CKRDY_R(crate::FieldReader<bool, bool>); +impl CKRDY_R { + pub(crate) fn new(bits: bool) -> Self { + CKRDY_R(crate::FieldReader::new(bits)) + } +} +impl core::ops::Deref for CKRDY_R { + type Target = crate::FieldReader<bool, bool>; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub struct CKRDY_W<'a> { + w: &'a mut W, +} +impl<'a> CKRDY_W<'a> { + #[doc = r"Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.bit(true) + } + #[doc = r"Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.bit(false) + } + #[doc = r"Writes raw bits to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits = (self.w.bits & !0x01) | (value as u8 & 0x01); + self.w + } +} +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 0x01) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&mut self) -> CKRDY_W { + CKRDY_W { w: self } + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + #[inline(always)] + fn reset_value() -> Self::Ux { + 0x01 + } +} |